Christer Svensson

According to our database, Christer Svensson authored at least 83 papers between 1983 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2020

A 10b 1GS/s Inverter-Based Pipeline ADC in 65nm CMOS.

Timmy Sundström, Javad Bagheri Asli, Christer Svensson, Atila Alvandpour

Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020

2014

Power Consumption of Integrated Low-Power Receivers.

Emil Nilsson, Christer Svensson

IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain.

Nasim Farahini, Ahmed Hemani, Anders Lansner, Fabien Clermidy, Christer Svensson

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Ultra Low Power Wake-Up Radio Using Envelope Detector and Transmission Line Voltage Transformer.

Emil Nilsson, Christer Svensson

IEEE J. Emerg. Sel. Topics Circuits Syst., 2013

Resource efficient implementation of a 10Gb/s radio receiver baseband in FPGA.

Christer Svensson, Zhongxia Simon He, Herbert Zirath, Lei Bao, Jingjing Chen

Proceedings of the 10th FPGAworld Conference, 2013

2012

Analysis of a 5.5-V Class-D Stage Used in +30-dBm Outphasing RF PAs in 130- and 65-nm CMOS.

Jonas Fritzin, Christer Svensson, Atila Alvandpour

IEEE Trans. Circuits Syst. II Express Briefs, 2012

Design and Analysis of a Class-D Stage With Harmonic Suppression.

Jonas Fritzin, Christer Svensson, Atila Alvandpour

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2011

A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS.

Timmy Sundström, Christer Svensson, Atila Alvandpour

IEEE J. Solid State Circuits, 2011

A +32 dBm 1.85 GHz class-D outphasing RF PA in 130nm CMOS for WCDMA/LTE.

Jonas Fritzin, Christer Svensson, Atila Alvandpour

Proceedings of the 37th European Solid-State Circuits Conference, 2011

Power consumption bounds for SAR ADCs.

Dai Zhang, Christer Svensson, Atila Alvandpour

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

Envelope detector sensitivity and blocking characteristics.

Emil Nilsson, Christer Svensson

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

A 2.4 GS/s, 4.9 ENOB at Nyquist, single-channel pipeline ADC in 65nm CMOS.

Timmy Sundström, Christer Svensson, Atila Alvandpour

Proceedings of the 36th European Solid-State Circuits Conference, 2010

A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS.

Jonas Fritzin, Christer Svensson, Atila Alvandpour

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters.

Timmy Sundström, Boris Murmann, Christer Svensson

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008

2.6 Gb/s over a four-drop bus using an adaptive 12-tap DFE.

Henrik Fredriksson, Christer Svensson

Proceedings of the ESSCIRC 2008, 2008

2007

Analog Power Modelling.

Christer Svensson

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

3-Gb/s, Single-ended Adaptive Equalization of Bidirectional Data over a Multi-drop Bus.

Henrik Fredriksson, Christer Svensson

Proceedings of the International Symposium on System-on-Chip, 2007

A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS.

Rashad Ramzan, Stefan Back Andersson, Jerzy J. Dabrowski, Christer Svensson

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Multiband direct RF-sampling receiver front-end for WLAN in 0.13 μm CMOS.

Stefan Back Andersson, Rashad Ramzan, Jerzy J. Dabrowski, Christer Svensson

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006

A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency.

Peter Caputa, Christer Svensson

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

An on-chip delay- and skew-insensitive multicycle communication scheme.

Peter Caputa, Christer Svensson

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

SC filter for RF down conversion with wideband image rejection.

Stefan Back Andersson, Jerzy J. Dabrowski, Christer Svensson, J. Konopacki

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Well-behaved global on-chip interconnect.

Peter Caputa, Christer Svensson

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A 2.4-GHz RF sampling receiver front-end in 0.18-μm CMOS.

Darius Jakonis, Kalle Folkesson, Jerzy J. Dabrowski, Patrik Eriksson, Christer Svensson

IEEE J. Solid State Circuits, 2005

Synchronous latency-insensitive design for multiple clock domain.

Anders Edman, Christer Svensson, Behzad Mesgarzadeh

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

A high-level dynamic-error model of a pipelined analog-to-digital converter.

Kalle Folkesson, Christer Svensson, B. Knuthammar, A. Dreyfert

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility study.

Henrik Fredriksson, Christer Svensson

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Robust multi-phase clock generation with reduced jitter.

Kalle Folkesson, Christer Svensson

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

A scalable and robust rail-to-rail delay cell for DLLs.

Håkan Bengtson, Christer Svensson

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies.

Peter Caputa, Henrik Fredriksson, Martin Hansson, Stefan Back Andersson, Atila Alvandpour, Christer Svensson

Proceedings of the Integrated Circuit and System Design, 2004

A new mesochronous clocking scheme for synchronization in SoC.

Behzad Mesgarzadeh, Christer Svensson, Atila Alvandpour

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2 GB/S decision feedback equalizer in 3.3 V 0.35 µM CMOS.

Håkan Bengtson, Christer Svensson

Proceedings of the Second IASTED International Conference on Circuits, 2004

A low-swing single-ended L1 cache bus technique for sub-90nm technologies.

Peter Caputa, Mark A. Anders, Christer Svensson, Ram K. Krishnamurthy, Shekhar Borkar

Proceedings of the 33rd European Solid-State Circuits Conference, 2004

Timing closure through a globally synchronous, timing partitioned design methodology.

Anders Edman, Christer Svensson

Proceedings of the 41th Design Automation Conference, 2004

Synchronous Latency Insensitive Design.

Christer Svensson

Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

2003

A 1.6 GHz downconversion sampling mixer in CMOS.

Darius Jakonis, Christer Svensson

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Bitline leakage equalization for sub-100nm caches.

Atila Alvandpour, Dinesh Somasekhar, Ram Krishnamurthy, Vivek De, Shekhar Borkar, Christer Svensson

Proceedings of the ESSCIRC 2003, 2003

Full-custom vs. standard-cell design flow: an adder case study.

Henrik Eriksson, Per Larsson-Edefors, Tomas Henriksson, Christer Svensson

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Electrical interconnects revitalized.

Christer Svensson

IEEE Trans. Very Large Scale Integr. Syst., 2002

Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract).

Stefan Rusu, Manoj Sachdev, Christer Svensson, Bram Nauta

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

A 1 GHz linearized CMOS track-and-hold circuit.

Darius Jakonis, Christer Svensson

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Application of Knowledge-based System in a B-to-B Environment.

Martin Malis, Christer Svensson, Lars Hvam

Proceedings of the Internet and Multimedia Systems and Applications, 2002

2001

Optimum voltage swing on on-chip and off-chip interconnect.

Christer Svensson

IEEE J. Solid State Circuits, 2001

A low-power 416-lag 1.5-b 0.5-TMAC correlator in 0.6-μm CMOS.

Anders Edman, Jacob Christensen, Anders Emrich, Christer Svensson

IEEE J. Solid State Circuits, 2001

Modeling of dynamic errors in algorithmic A/D converters.

Kalle Folkesson, Christer Svensson, Jan-Erik Eklund

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

3V CMOS 0.35 µ transimpedance receiver for optical applications.

Håkan Bengtson, Christer Svensson

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

Pulsewidth control loop in high-speed CMOS clock buffers.

Fenghao Mu, Christer Svensson

IEEE J. Solid State Circuits, 2000

Cosmic-ray soft error rate characterization of a standard 0.6-μm CMOS process.

Peter Hazucha, Christer Svensson, Stephen A. Wender

IEEE J. Solid State Circuits, 2000

Optimized test circuits for SER characterization of a manufacturing process.

Peter Hazucha, Christer Svensson

IEEE J. Solid State Circuits, 2000

Low power mixed analog-digital signal processing.

Mattias Duppils, Christer Svensson

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

GLMC: interconnect length estimation by growth-limited multifold clustering.

Atila Alvandpour, Per Larsson-Edefors, Christer Svensson

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

A layout-based schematic method for very high-speed CMOS cell design.

Fenghao Mu, Christer Svensson

IEEE Trans. Very Large Scale Integr. Syst., 1999

Vector Transfer by Self-Tested Self-Synchronization for Parallel Systems.

Fenghao Mu, Christer Svensson

IEEE Trans. Parallel Distributed Syst., 1999

Methodology of layout based schematic and its usage in efficient high performance CMOS design.

Fenghao Mu, Christer Svensson

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

High speed multistage CMOS clock buffers with pulse width control loop.

Fenghao Mu, Christer Svensson

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

High speed interface for system-on-chip design by self-tested self-synchronization.

Fenghao Mu, Christer Svensson

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A novel mixed analog/digital MAC unit implemented with SC technique suitable for fully programmable narrow-band FIR filter applications.

Mattias Duppils, Jan-Erik Eklund, Christer Svensson

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

A leakage-tolerant multi-phase keeper for wide domino circuits.

Atila Alvandpour, Per Larsson-Edefors, Christer Svensson

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

Time resolution of NMOS sampling switches used on low-swing signals.

Henrik O. Johansson, Christer Svensson

IEEE J. Solid State Circuits, 1998

Low power and low voltage CMOS digital circuit techniques.

Christer Svensson, Atila Alvandpour

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits.

Atila Alvandpour, Per Larsson-Edefors, Christer Svensson

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Self-Synchronized Vector Transfer for High Speed Parallel Systems.

Fenghao Mu, Christer Svensson

Proceedings of the International Conference on Parallel and Distributed Systems, 1998

Efficient High-Speed CMOS Design by Layout Based Schematic Method.

Fenghao Mu, Christer Svensson

Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997

New single-clock CMOS latches and flipflops with improved speed and power savings.

Jiren Yuan, Christer Svensson

IEEE J. Solid State Circuits, 1997

1996

VLSI implementation of a focal plane image processor-a realization of the near-sensor image processing concept.

Jan-Erik Eklund, Christer Svensson, Anders Åström

IEEE Trans. Very Large Scale Integr. Syst., 1996

1994

Power consumption estimation in CMOS VLSI chips.

Dake Liu, Christer Svensson

IEEE J. Solid State Circuits, June, 1994

Impact of clock slope on true single phase clocked (TSPC) CMOS circuits.

Patrik Larsson, Christer Svensson

IEEE J. Solid State Circuits, June, 1994

Noise in digital dynamic CMOS circuits.

Patrik Larsson, Christer Svensson

IEEE J. Solid State Circuits, June, 1994

5.8Gb/s 16: 1 Multiplexer and 1: 16 Demultiplexer Using 1.2µm BiCMOS.

Jacob Midtgaard, Christer Svensson

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Single-chip image sensors with a digital processor array.

Robert Forchheimer, Keping Chen, Christer Svensson, Anders Ödmark

J. VLSI Signal Process., 1993

Ultra high speed CMOS design.

Christer Svensson, Jiren Yuan

Proceedings of the VLSI 93, 1993

A sensor array for phase and amplitude detection of synchronous modulated light sources.

Christer Jansson, Christer Svensson

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

System Level Policies for Fault Tolerance Issues in the FERMI Project.

A. Dell'Acqua, M. Hansen, Sami J. Inkinen, B. Lofstedt, J. P. Vanuxem, Christer Svensson, Jiren Yuan, H. Hentzell, L. Del Buono, J. David, J. F. Genat, H. Lebbolo, O. LeDortz, P. Nayman, Aurore Savoy-Navarro, R. Zitoun, Cesare Alippi, Luca Breveglieri, Luigi Dadda, Vincenzo Piuri, Fabio Salice, Mariagiovanna Sami, Renato Stefanelli, P. Cattaneo, G. Fumagalli, G. Goggi, Simona Brigati, Umberto Gatti, Franco Maloberti, Guido Torelli, P. Carlson, A. Kerek, Goran Appelquist, S. Berglund, C. Bohm, Magnus Engström, N. Yamdagni, Rolf Sundblad, I. Höglund, S. T. Persson

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992

Performance of Synchronous and Asynchronous Schemes for VLSI Systems.

Morteza Afghahi, Christer Svensson

IEEE Trans. Computers, 1992

1990

A unified single-phase clocking scheme for VLSI systems.

Morteza Afghahi, Christer Svensson

IEEE J. Solid State Circuits, February, 1990

Single-Chip High-Speed Computation of Optical Flow.

Per-Erik Danielsson, Pär Emanuelsson, Keping Chen, Per Ingelhag, Christer Svensson

Proceedings of IAPR Workshop on Machine Vision Applications, 1990

1989

High-speed CMOS circuit technique.

Jiren Yuan, Christer Svensson

IEEE J. Solid State Circuits, February, 1989

1988

Switch-level simulation and the pass transistor EXOR gate.

Christer Svensson, Robert Tjärnström

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1987

Fully Dynamic Switch-Level Simulation of CMOS Circuits.

Rolf Sundblad, Christer Svensson

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

Guest editorial.

Christer Svensson

Integr., 1987

1986

Signal resynchronization in VLSI systems.

Christer Svensson

Integr., 1986

1984

NORCHIP, a silicon brokers model.

Ole Olesen, Christer Svensson

Integr., 1984

1983

VLSI physics.

Christer Svensson

Integr., 1983