Chris J. Nicol

According to our database1, Chris J. Nicol authored at least 8 papers between 1993 and 2000.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2000
A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP.
IEEE J. Solid State Circuits, 2000

1998
Reconfigurable hardware for efficient implementation of programmable FIR filters.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

1997
A low-power 128-tap digital adaptive equalizer for broadband modems.
IEEE J. Solid State Circuits, 1997

Low power multiplication for FIR filters.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

1996
A scalable pipelined architecture for fast buffer SRAMs.
IEEE J. Solid State Circuits, 1996

Transition reduction in carry-save adder trees.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1994
Application Specific Memories for ATM Packet Switching.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
A Systolic Architecture for High Speed Pipelined Memories.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993


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