Chris J. Myers
Orcid: 0000-0002-8762-8444
According to our database1,
Chris J. Myers
authored at least 142 papers
between 1993 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
PhageBox: An Open Source Digital Microfluidic Extension With Applications for Phage Discovery.
IEEE Trans. Biomed. Eng., January, 2024
Specifications of standards in systems and synthetic biology: status, developments, and tools in 2024.
J. Integr. Bioinform., 2024
Proceedings of the Quantitative Evaluation of Systems and Formal Modeling and Analysis of Timed Systems, 2024
2023
PLoS Comput. Biol., December, 2023
ACM J. Emerg. Technol. Comput. Syst., July, 2023
Specifications of standards in systems and synthetic biology: status and developments in 2022 and the COMBINE meeting 2022.
J. Integr. Bioinform., March, 2023
J. Integr. Bioinform., March, 2023
Proceedings of the Quantitative Evaluation of Systems - 20th International Conference, 2023
2022
BioSimulators: a central registry of simulation engines and services for recommending specific tools.
Nucleic Acids Res., 2022
BioSimulators: a central registry of simulation engines and services for recommending specific tools.
CoRR, 2022
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2022
2021
Specifications of standards in systems and synthetic biology: status and developments in 2021.
J. Integr. Bioinform., 2021
J. Integr. Bioinform., 2021
J. Integr. Bioinform., 2021
2020
The first 10 years of the international coordination network for standards in systems and synthetic biology (COMBINE).
J. Integr. Bioinform., 2020
Systems Biology Markup Language (SBML) Level 3 Package: Distributions, Version 1, Release 1.
J. Integr. Bioinform., 2020
Specifications of standards in systems and synthetic biology: status and developments in 2020.
J. Integr. Bioinform., 2020
J. Integr. Bioinform., 2020
2019
Proceedings of the Automated Reasoning for Systems Biology and Medicine, 2019
Simul., 2019
Specifications of Standards in Systems and Synthetic Biology: Status and Developments in 2019.
J. Integr. Bioinform., 2019
J. Integr. Bioinform., 2019
The Systems Biology Markup Language (SBML): Language Specification for Level 3 Version 2 Core Release 2.
J. Integr. Bioinform., 2019
Briefings Bioinform., 2019
Proceedings of the Computer Aided Verification - 31st International Conference, 2019
2018
Specifications of Standards in Systems and Synthetic Biology: Status and Developments in 2017.
J. Integr. Bioinform., 2018
The Systems Biology Markup Language (SBML): Language Specification for Level 3 Version 2 Core.
J. Integr. Bioinform., 2018
The Systems Biology Markup Language (SBML): Language Specification for Level 3 Version 1 Core.
J. Integr. Bioinform., 2018
J. Integr. Bioinform., 2018
2017
Proceedings of the 2017 Winter Simulation Conference, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
IEEE Trans. Biomed. Eng., 2016
An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis.
Sci. Comput. Program., 2016
Specifications of Standards in Systems and Synthetic Biology: Status and Developments in 2016.
J. Integr. Bioinform., 2016
IEEE Des. Test, 2016
2015
IEEE Trans. Multi Scale Comput. Syst., 2015
J. Integr. Bioinform., 2015
J. Integr. Bioinform., 2015
Systems Biology Markup Language (SBML) Level 2 Version 5: Structures and Facilities for Model Definitions.
J. Integr. Bioinform., 2015
Bioinform., 2015
Proceedings of the NASA Formal Methods - 7th International Symposium, 2015
2014
ACM J. Emerg. Technol. Comput. Syst., 2014
ACM J. Emerg. Technol. Comput. Syst., 2014
Proceedings of the 2014 Spring Simulation Multiconference, 2014
LEMA: A tool for the formal verification of digitally-intensive analog/mixed-signal circuits.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the Formal Methods for Industrial Critical Systems, 2014
2013
Proceedings of the 2013 Forum on specification and Design Languages, 2013
Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
IEEE Des. Test Comput., 2012
Proceedings of the Model Checking Software - 19th International Workshop, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the 2012 IEEE/ACM Third International Conference on Cyber-Physical Systems, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Using decision diagrams to compactly represent the state space for explicit model checking.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012
Proceedings of the 2012 IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology, 2012
Proceedings of the Computer Aided Verification - 24th International Conference, 2012
2011
IEEE ACM Trans. Comput. Biol. Bioinform., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the 13th IEEE International Symposium on High-Assurance Systems Engineering, 2011
Erlang-delayed stochastic chemical kinetic formalism for efficient analysis of biological systems with non-elementary reaction effects.
Proceedings of the ACM International Conference on Bioinformatics, 2011
2010
Temperature Control of Fimbriation Circuit Switch in Uropathogenic <i>Escherichia coli</i>: Quantitative Analysis via Automated Model Abstraction.
PLoS Comput. Biol., 2010
Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces.
Int. J. Found. Comput. Sci., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the ACM/IEEE 1st International Conference on Cyber-Physical Systems, 2010
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010
2009
A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation.
IPSJ Trans. Syst. LSI Des. Methodol., 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Production-Passage-Time Approximation: A New Approximation Method to Accelerate the Simulation Process of Enzymatic Reactions.
J. Comput. Biol., 2008
A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper).
Proceedings of the 8th International Conference on Application of Concurrency to System Design (ACSD 2008), 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007
Proceedings of the Automated Technology for Verification and Analysis, 2007
Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces.
Proceedings of the Automated Technology for Verification and Analysis, 2007
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Trans. Comp. Sys. Biology, 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Abstracted Stochastic Analysis of Type 1 Pili Expression in E.coli.
Proceedings of the 2006 International Conference on Bioinformatics & Computational Biology, 2006
Proceedings of the Automated Technology for Verification and Analysis, 2006
Proceedings of the Sixth International Conference on Computer and Information Technology (CIT 2006), 2006
2005
IEICE Trans. Inf. Syst., 2005
Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation.
IEICE Trans. Inf. Syst., 2005
Proceedings of the First Workshop on Formal Verification of Analog Circuits, 2005
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005
2004
Proceedings of the Automated Technology for Verification and Analysis: Second International Conference, 2004
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004
2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Proceedings of the Theory and Practice of Timed Systems, 2002
Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method.
Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the Computer Aided Verification, 14th International Conference, 2002
2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the 2001 IEEE Information Theory Workshop, 2001
Proceedings of the Computer Aided Verification, 13th International Conference, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001
Proceedings of ASP-DAC 2001, 2001
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001
A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems.
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001
Asynchronous circuit design.
Wiley, ISBN: 978-0-471-41543-5, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
1999
POSET timing and its application to the synthesis and verification of gate-level timed circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Proceedings of the IEEE International Conference On Computer Design, 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999
1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Proceedings of the Computer Aided Verification, 10th International Conference, 1998
Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998
1997
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997
1995
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995
1994
Proceedings of the Computer Aided Verification, 6th International Conference, 1994
1993
IEEE Trans. Very Large Scale Integr. Syst., 1993