Chris Fallin

Orcid: 0000-0002-6733-1803

Affiliations:
  • Fastly, San Francisco, CA, USA


According to our database1, Chris Fallin authored at least 19 papers between 2010 and 2024.

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Bibliography

2024
Hardware-Assisted Fault Isolation: Going Beyond the Limits of Software-Based Sandboxing.
IEEE Micro, 2024

Lightweight, Modular Verification for WebAssembly-to-Native Instruction Selection.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Going beyond the Limits of SFI: Flexible and Secure Hardware-Assisted In-Process Isolation with HFI.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2020
Safe, Flexible Aliasing with Deferred Borrows.
Proceedings of the 34th European Conference on Object-Oriented Programming, 2020

2018
RowClone: Accelerating Data Movement and Initialization Using DRAM.
CoRR, 2018

2016
A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate.
Parallel Comput., 2016

RowHammer: Reliability Analysis and Security Implications.
CoRR, 2016

Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing.
CoRR, 2016

2014
Design and Evaluation of Hierarchical Rings with Deflection Routing.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

The heterogeneous block architecture.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013
RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012
On-chip networks from a networking perspective: congestion and scalability in many-core interconnects.
Proceedings of the ACM SIGCOMM 2012 Conference, 2012

HAT: Heterogeneous Adaptive Throttling for On-Chip Networks.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

2011
Parallel application memory scheduling.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Memory power management via dynamic voltage/frequency scaling.
Proceedings of the 8th International Conference on Autonomic Computing, 2011

CHIPPER: A low-complexity bufferless deflection router.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010
Next generation on-chip networks: what kind of congestion control do we need?
Proceedings of the 9th ACM Workshop on Hot Topics in Networks. HotNets 2010, Monterey, CA, USA - October 20, 2010


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