Chris Diorio

Affiliations:
  • University of Washington, Seattle, Washington, USA


According to our database1, Chris Diorio authored at least 35 papers between 1994 and 2008.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2008
A 3 µW CMOS True Random Number Generator With Adaptive Floating-Gate Offset Cancellation.
IEEE J. Solid State Circuits, 2008

A micro-power neural spike detector and feature extractor in .13μm CMOS.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Self-tuning adaptive delay sequential elements.
Microelectron. J., 2007

A compact pulse-based charge pump in 0.13 μm CMOS.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Design and Application of Adaptive Delay Sequential Elements.
IEEE Trans. Very Large Scale Integr. Syst., 2006

2005
In-Circuit Self-Tuning of Clock Latencies.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A reconfigurable VLSI learning array.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004
A 19.2 GOPS mixed-signal filter with floating-gate adaptation.
IEEE J. Solid State Circuits, 2004

Design of ultra-low-cost UHF RFID tags for supply chain applications.
IEEE Commun. Mag., 2004

On-Chip Compensation of Device-Mismatch Effects in Analog VLSI Neural Networks.
Proceedings of the Advances in Neural Information Processing Systems 17 [Neural Information Processing Systems, 2004

Timing Correction and Optimization with Adaptive Delay Sequential Element.
Proceedings of the 2004 Design, 2004

2003
Hidden-articulator Markov models for speech recognition.
Speech Commun., 2003

A 300-MS/s 14-bit digital-to-analog converter in logic CMOS.
IEEE J. Solid State Circuits, 2003

Computer Electronics Meet Animal Brains.
Computer, 2003

A 19.2GOPS, 20mW adaptive FIR filter.
Proceedings of the ESSCIRC 2003, 2003

2002
Competitive learning with floating-gate circuits.
IEEE Trans. Neural Networks, 2002

Prolog to adaptive CMOS: from biological inspiration to systems-on-a-chip.
Proc. IEEE, 2002

Adaptive CMOS: from biological inspiration to systems-on-a-chip.
Proc. IEEE, 2002

Adaptive Quantization and Density Estimation in Silicon.
Proceedings of the Advances in Neural Information Processing Systems 15 [Neural Information Processing Systems, 2002

Field-Programmable Learning Arrays.
Proceedings of the Advances in Neural Information Processing Systems 15 [Neural Information Processing Systems, 2002

2001
A mixed-signal approach to high-performance low-power linear filters.
IEEE J. Solid State Circuits, 2001

Learning Spike-Based Correlations and Conditional Probabilities in Silicon.
Proceedings of the Advances in Neural Information Processing Systems 14 [Neural Information Processing Systems: Natural and Synthetic, 2001

2000
A Silicon Primitive for Competitive Learning.
Proceedings of the Advances in Neural Information Processing Systems 13, 2000

Hidden-articulator Markov models: performance improvements and robustness to noise.
Proceedings of the Sixth International Conference on Spoken Language Processing, 2000

An FPGA-Based Array Processor for an Ionospheric-Imaging Radar.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999
Synthesis of multiple-input translinear element networks.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Floating-gate devices: they are not just for digital memories any more.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Adaptive Circuits Using pFET Floating-Gate Devices.
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999

1998
Impact Ionization and Hot-Electron Injection Derived Consistently from Boltzmann Transport.
VLSI Design, 1998

A low-noise, GaAs/AlGaAs, microwave frequency-synthesizer IC.
IEEE J. Solid State Circuits, 1998

1995
A vMOS Soft-Maximum Current Mirror.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Single Transistor Learning Synapse with Long Term Storage.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A High-Resolution Non-Volatile Analog Memory Cell.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
A Silicon Axon.
Proceedings of the Advances in Neural Information Processing Systems 7, 1994

Single Transistor Learning Synapses.
Proceedings of the Advances in Neural Information Processing Systems 7, 1994


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