Chris Borrelli
According to our database1,
Chris Borrelli
authored at least 2 papers
between 2016 and 2017.
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Bibliography
2017
A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET.
IEEE J. Solid State Circuits, 2017
2016
A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016