Chotei Zukeran

According to our database, Chotei Zukeran authored at least 6 papers between 1986 and 2001.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2001

Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits.

Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, Chotei Zukeran

Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

1998

Reconfigurable Current-Mode Multiple-Valued Residue Arithmetic Circuits.

Katsuhiko Shimabukuro, Chotei Zukeran

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

1992

A universal literal circuit and its application to quaternary logic networks.

Chotei Zukeran, Yasunori Nagata, Chushin Afuso, Makoto Honda, Yutaka Nagamine

Syst. Comput. Jpn., 1992

1990

A State Assignment for p-Valued Sequential Machines.

Yasunori Nagata, Chotei Zukeran, Chushin Afuso

Syst. Comput. Jpn., 1990

1987

Design of micropower CMOS quaternary memory circuits.

Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi

Syst. Comput. Jpn., 1987

1986

Design of low-power quaternary CMOS logic circuits.

Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi

Syst. Comput. Jpn., 1986