Chong S. Rim

According to our database1, Chong S. Rim authored at least 11 papers between 1989 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2010
Adaptive Mixed Scheduling for Correcting Errors in Trapping Sets of LDPC Codes.
IEEE Commun. Lett., 2010

1999
SEGRA: a very fast general area router for multichip modules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

A Graph Theoretical Approach for the Yield Enhancement of Reconfigurable VLSI/WSI Arrays.
Discret. Appl. Math., 1999

Circuit partitioning by quadratic Boolean programming for reconfigurable circuit boards.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1997
A simple and effective greedy multilayer router for MCMs.
Proceedings of the 1997 International Symposium on Physical Design, 1997

1995
A Block Matching Algorithm with 16: 1 Subsampling and Its Hardware Design.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Automatic Functional Cell Generation in the Sea-of-Gates Layout Style.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1992
General Circular Permutation Layout.
Math. Syst. Theory, 1992

1989
Exact algorithms for multilayer topological via minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Graph Bipartization and via Minimization.
SIAM J. Discret. Math., 1989


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