Chizu Matsumoto

According to our database, Chizu Matsumoto authored at least 3 papers between 2009 and 2013.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of four.

2013

Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs.

Chizu Matsumoto, Yuichi Hamamura, Michinobu Nakao, Kaname Yamasaki, Yoshikazu Saito, Shun'ichi Kaneko

IEICE Trans. Electron., 2013

2011

A New Critical Area Simulation Algorithm and Its Application for Failing Bit Analysis.

Chizu Matsumoto, Yuichi Hamamura, Yoshiyuki Tsunoda, Hiroshi Uozaki, Isao Miyazaki, Shiro Kamohara, Yoshiyuki Kaneko, Kenji Kanamitsu

IEICE Trans. Electron., 2011

2009

Development of an Enterprise-Wide Yield Management System Using Critical Area Analysis for High-Product-Mix Semiconductor Manufacturing.

Yuichi Hamamura, Chizu Matsumoto, Yoshiyuki Tsunoda, Koji Kamoda, Yoshio Iwata, Kenji Kanamitsu, Daisuke Fujiki, Fujihiko Kojika, Hiromi Fujita, Yasuo Nakagawa, Shun'ichi Kaneko

IEICE Trans. Electron., 2009