Chittarsu Raghunandan

According to our database, Chittarsu Raghunandan authored at least 5 papers between 2007 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2008

Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.

Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

Bus encoding schemes for minimizing delay in VLSI interconnects.

K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme.

K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN).

Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects.

Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007