Chirn Chye Boon

According to our database, Chirn Chye Boon authored at least 68 papers between 2004 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

A 0.6 V, 1.74 mW, 2.9 dB NF Inductorless Wideband LNA in 28-nm CMOS Exploiting Noise Cancellation and Current Reuse.

Zhe Liu, Chirn Chye Boon, Yangtao Dong

IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024

2023

A Single-Channel Voltage-Scalable 8-GS/s 8-b >37.5-dB SNDR Time-Domain ADC With Asynchronous Pipeline Successive Approximation in 28-nm CMOS.

Qian Chen, Chirn Chye Boon, Qing Liu, Yuan Liang

IEEE J. Solid State Circuits, 2023

A Single-Channel 10GS/s 8b>36.4d8 SNDR Time-Domain ADC Featuring Loop-Unrolled Asynchronous Successive Approximation in 28nm CMOS.

Oian Chen, Yuan Liang, Chirn Chye Boon, Oing Liu

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 2.4dB NF +4.1dBm IIP3 Differential Dual-Feedforward-Based Noise-Cancelling LNTA With Complementary NMOS and PMOS Configuration.

Zhe Liu, Chirn Chye Boon, Yangtao Dong, Kaituo Yang

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

A 0.092-mm² 2-12-GHz Noise-Cancelling Low-Noise Amplifier With Gain Improvement and Noise Reduction.

Zhe Liu, Chirn Chye Boon

IEEE Trans. Circuits Syst. II Express Briefs, 2022

An Equivalent-Time Sampling Millimeter-Wave Ultra-Wideband Radar Pulse Digitizer in CMOS.

Gibran Limi Jaya, Chirn Chye Boon, Shoushun Chen, Liter Siek

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 0.6 V 4 GS/s -56.4 dB THD Voltage-to-Time Converter in 28 nm CMOS.

Qian Chen, Chirn Chye Boon, Yuan Liang

IEEE Access, 2022

A Hybrid Coupler-First 5GHz Noise-Cancelling Dual-Mode Receiver with +10dBm in-Band IIP3 in Current-Mode and 1.7dB NF in Voltage-Mode.

Kaituo Yang, Chirn Chye Boon, Zhe Liu, Jiaming Piao, Ting Guo, Yangtao Dong, Chenyang Li, Ao Zhou, Zhijie Yang, Xiaoying Wang, Yufeng Liu

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 0.0078mm2 3.4mW Wideband Positive-feedback-Based Noise-Cancelling LNA in 28nm CMOS Exploiting G_m Boosting.

Zhe Liu, Chirn Chye Boon, Chenyang Li, Kaituo Yang, Yangtao Dong, Ting Guo

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 2-GHz Dual-Path Sub-Sampling PLL with Ring VCO Phase Noise Suppression.

Yangtao Dong, Chirn Chye Boon, Kaituo Yang, Zhe Liu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

A Bidirectional Nonlinearly Coupled QVCO With Passive Phase Interpolation for Multiphase Signals Generation.

Yangtao Dong, Chirn Chye Boon, Xin Ding, Chenyang Li, Zhe Liu

IEEE Trans. Very Large Scale Integr. Syst., 2021

A 2.4-6 GHz Broadband GaN Power Amplifier for 802.11ax Application.

Bei Liu, Chirn Chye Boon, Mengda Mao, Pilsoon Choi, Ting Guo

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Parallel Sliding-IF Receiver Front-End With Sub-2-dB Noise Figure for 5-6-GHz WLAN Carrier Aggregation.

Kaituo Yang, Xiang Yi, Chirn Chye Boon, Zhipeng Liang, Guangyin Feng, Chenyang Li, Bei Liu

IEEE J. Solid State Circuits, 2021

A Low-Power Quadrature LO Generator With Mutual Power-Supply Rejection Technique.

Ao Zhou, Xin Ding, Chirn Chye Boon, Liter Siek, Yuan Liang, Yangtao Dong

IEEE Access, 2021

A 20-80 MHz Continuously Tunable Gm-C Low-Pass Filter for Ultra-Low Power WBAN Receiver Front-End.

Xiaoying Wang, Chirn Chye Boon, Kaituo Yang, Lingshan Kong

IEEE Access, 2021

Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique.

Lingshan Kong, Yong Chen, Haohong Yu, Chirn Chye Boon, Pui-In Mak, Rui Paulo Martins

IEEE Access, 2021

A 1.75dB-NF 25mW 5GHz Transformer-Based Noise- Cancelling CMOS Receiver Front-End.

Kaituo Yang, Chirn Chye Boon, Guangyin Feng, Chenyang Li, Zhe Liu, Ting Guo, Xiang Yi, Yangtao Dong, Ao Zhou, Xiaoying Wang

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Millimetre-Wave and Terahertz Antennas and Directional Coupler Enabled by Wafer-Level Packaging Platform with Interposer.

Yuan Liang, Chirn Chye Boon, Qian Chen, Yangtao Dong

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Cross-Coupled Pair Regeneration Based dB-Linear Programable Gain Amplifier with THD Enhancement.

Yangtao Dong, Chirn Chye Boon, Kaituo Yang, Ao Zhou, Xin Ding

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

An Inverted Ring Oscillator Noise-Shaping Time-to-Digital Converter With In-Band Noise Reduction and Coherent Noise Cancellation.

Xiang Yi, Zhipeng Liang, Chirn Chye Boon, Guangyin Feng, Fanyi Meng, Kaituo Yang

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Design of a Wideband Variable-Gain Amplifier With Self-Compensated Transistor for Accurate dB-Linear Characteristic in 65 nm CMOS Technology.

Lingshan Kong, Hang Liu, Xi Zhu, Chirn Chye Boon, Chenyang Li, Zhe Liu, Kiat Seng Yeo

IEEE Trans. Circuits Syst., 2020

Compact Switched-Capacitor Power Detector With Frequency Compensation in 65-nm CMOS.

Chenyang Li, Chirn Chye Boon, Xiang Yi, Zhipeng Liang, Kaituo Yang

IEEE Access, 2020

A 0.024-mm² 45.4-GHz-Bandwidth Unity-Gain Output Driver with SDD22<-10dB up to 35 GHz.

Yong Chen, Pui-In Mak, Chirn Chye Boon, Rui Paulo Martins

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A 6bit 1.2GS/s Symmetric Successive Approximation Energy-Efficient Time-to-Digital Converter in 40nm CMOS.

Qian Chen, Yuan Liang, Chirn Chye Boon

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Multi-Channel FSK Inter/Intra-Chip Communication by Exploiting Field-Confined Slow-Wave Transmission Line.

Qian Chen, Chirn Chye Boon, Xueyong Zhang, Chenyang Li, Yuan Liang, Zhe Liu, Ting Guo

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A 3GS/s Highly Linear Energy Efficient Constant-Slope Based Voltage-to-Time Converter.

Qian Chen, Yuan Liang, Bongjin Kim, Chirn Chye Boon

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Monolithically Integrated GaN+CMOS Logic Circuits Design and Electro-Thermal Analysis for High-Voltage Applications.

Pilsoon Choi, Bugra Kanargi, Kenneth E. Lee, Chirn Chye Boon, Evelyn Wang, Chuan Seng Tan, Dimitri A. Antoniadis, Eugene A. Fitzgerald

Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2020

2019

Design and Analysis of $D$ -Band On-Chip Modulator and Signal Source Based on Split-Ring Resonator.

Yuan Liang, Chirn Chye Boon, Chenyang Li, Xiao-Lan Tang, Herman Jalli Ng, Dietmar Kissinger, Yong Wang, Qingfeng Zhang, Hao Yu

IEEE Trans. Very Large Scale Integr. Syst., 2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.

Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber

IEEE Trans. Very Large Scale Integr. Syst., 2019

A 0.044-mm² 0.5-to-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB.

Haohong Yu, Yong Chen, Chirn Chye Boon, Chenyang Li, Pui-In Mak, Rui Paulo Martins

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Low-Noise, Positive-Input, Negative-Output Voltage Generator for Low-to-Moderate Driving Capacity Applications.

Devrishi Khanna, Chirn Chye Boon, Pilsoon Choi, Liter Siek, Bei Liu, Chenyang Li

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 0.0071-mm² 10.8ps_pp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis.

Yong Chen, Pui-In Mak, Zunsong Yang, Chirn Chye Boon, Rui Paulo Martins

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 24/77 GHz Dual-Band Receiver for Automotive Radar Applications.

Xiang Yi, Guangyin Feng, Zhipeng Liang, Cheng Wang, Bei Liu, Chenyang Li, Kaituo Yang, Chirn Chye Boon, Quan Xue

IEEE Access, 2019

Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique.

Lingshan Kong, Yong Chen, Haohong Yu, Quan Pan, Chirn Chye Boon, Pui-In Mak, Rui Paulo Martins

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS.

Arya Balachandran, Yong Chen, Chirn Chye Boon

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018

A 0.013-mm² 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS.

Arya Balachandran, Yong Chen, Chirn Chye Boon

IEEE Trans. Very Large Scale Integr. Syst., 2018

A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications.

Lingshan Kong, Yong Chen, Chirn Chye Boon, Pui-In Mak, Rui Paulo Martins

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin.

Yong Chen, Pui-In Mak, Chirn Chye Boon, Rui Paulo Martins

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A W-Band Switch-Less Dicke Receiver for Millimeter-Wave Imaging in 65 nm CMOS.

Guangyin Feng, Xiang Yi, Fanyi Meng, Chirn Chye Boon

IEEE Access, 2018

D-Band Surface-Wave Modulator and Signal Source with 40 dB Extinction Ratio and 3.7mW Output Power in 65 nm CMOS.

Yuan Liang, Hao Yu, Chirn Chye Boon, Chenyang Li, Dietmar Kissinger, Yong Wang

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017

Editorial.

Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson

IEEE Trans. Very Large Scale Integr. Syst., 2017

Pole-Converging Intrastage Bandwidth Extension Technique for Wideband Amplifiers.

Guangyin Feng, Chirn Chye Boon, Fanyi Meng, Xiang Yi, Kaituo Yang, Chenyang Li, Howard C. Luong

IEEE J. Solid State Circuits, 2017

2016

An on-chip integrated III-V / CMOS 125MSps 6-bit SAR ADC.

Sunny Sharma, Siau Ben Chiah, Xing Zhou, Chirn Chye Boon

Proceedings of the International Symposium on Integrated Circuits, 2016

2015

Cell-Based Variable-Gain Amplifiers With Accurate dB-Linear Characteristic in 0.18 µm CMOS Technology.

Hang Liu, Xi Zhu, Chirn Chye Boon, Xiaofeng He

IEEE J. Solid State Circuits, 2015

2014

A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology.

Xiang Yi, Chirn Chye Boon, Hang Liu, Jia-fu Lin, Wei Meng Lim

IEEE J. Solid State Circuits, 2014

Design and Analysis of a 2.4 GHz Hybrid Type Automatic amplitude Control VCO with Forward noise Reduction.

Y. X. Zhang, Chirn Chye Boon, Kiat Seng Yeo

J. Circuits Syst. Comput., 2014

A case for leveraging 802.11p for direct phone-to-phone communications.

Pilsoon Choi, Jason H. Gao, Nadesh Ramanathan, Mengda Mao, Shipeng Xu, Chirn Chye Boon, Suhaib A. Fahmy, Li-Shiuan Peh

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

2013

Cross-Coupled Current Conveyor Based CMOS Transimpedance Amplifier for Broadband Data Transmission.

Dandan Chen, Kiat Seng Yeo, Xiaomeng Shi, Manh Anh Do, Chirn Chye Boon, Wei Meng Lim

IEEE Trans. Very Large Scale Integr. Syst., 2013

Design of a fully integrated CMOS dual K- and W-band lumped wilkinson power divider.

Nan Huang, Xiang Yi, Chirn Chye Boon, Xiaojin Zhao, Junyi Sun, Guangyin Feng

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS.

Xiang Yi, Chirn Chye Boon, Hang Liu, Jia-fu Lin, Jian Cheng Ong, Wei Meng Lim

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A low-noise amplifier with continuously-tuned input matching frequency and output resonance frequency.

Xi Zhu, Chirn Chye Boon, Ayobami Iji, Yichuang Sun, Michael Heimlich

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

A Low-Power Single-Phase Clock Multiband Flexible Divider.

Manthena Vamshi Krishna, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo

IEEE Trans. Very Large Scale Integr. Syst., 2012

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector.

Yung Sern Tan, Kiat Seng Yeo, Chirn Chye Boon, Manh Anh Do

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A low power low phase noise dual-band multiphase VCO.

Juan Xie, Manthena Vamshi Krishna, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo

Microelectron. J., 2012

Implementations of Signal-Processing Algorithms for OFDM Systems.

Ming-Der Shieh, Yin-Tsung Hwang, Hanho Lee, Chirn Chye Boon, Zhiyuan Yan

J. Electr. Comput. Eng., 2012

A 100 GHz transformer-based varactor-less VCO with 11.2% tuning range in 65nm CMOS technology.

Xiang Yi, Chirn Chye Boon, Jia-fu Lin, Wei Meng Lim

Proceedings of the 38th European Solid-State Circuit conference, 2012

Design of quarter-wavelength resonator filters with coupling controllable paths.

Fanyi Meng, Kaixue Ma, Shanshan Xu, Kiat Seng Yeo, Chirn Chye Boon, Wei Meng Lim, Manh Anh Do

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

A 3.1-8 GHz CMOS UWB front-end receiver.

Ali Meaamar, Chirn Chye Boon, Xiaomeng Shi, Wei Meng Lim, Kiat Seng Yeo, Manh Anh Do

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback.

Zhenghao Lu, Kiat Seng Yeo, Wei Meng Lim, Manh Anh Do, Chirn Chye Boon

IEEE Trans. Very Large Scale Integr. Syst., 2010

A Wideband Low Power Low-Noise Amplifier in CMOS Technology.

Ali Meaamar, Chirn Chye Boon, Kiat Seng Yeo, Manh Anh Do

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler.

Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo, Chirn Chye Boon, Wei Meng Lim

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

An Energy-Aware CMOS Receiver Front End for Low-Power 2.4-GHz Applications.

Aaron V. T. Do, Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, Alper Cabuk

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4.

Manthena Vamshi Krishna, Juan Xie, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo, Aaron V. T. Do

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4.

Manthena Vamshi Krishna, Xuan Jie, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo, Aaron V. T. Do

Proceedings of the VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 2010

A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole.

Aaron V. T. Do, Chirn Chye Boon, Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo

Proceedings of the VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 2010

A 1-V CMOS ultralow-power receiver front end for the IEEE 802.15.4 standard using tuned passive mixer output pole.

Aaron V. T. Do, Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, Alper Cabuk

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

2005

Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction.

Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, Jianguo Ma

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

2004

RF CMOS low-phase-noise LC oscillator through memory reduction tail transistor.

Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, Jianguo Ma, Xiaoling Zhang

IEEE Trans. Circuits Syst. II Express Briefs, 2004