Chirag Sudarshan

Des. Autom. Embed. Syst., June, 2024

Analog In-Memory Computing Attention Mechanism for Fast and Energy-Efficient Large Language Models.

[BibT_eX]

[DOI]

CoRR, 2024

2023

Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.

[BibT_eX]

[DOI]

Matthias Jung

Andre Guntoro

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

FeFET versus DRAM based PIM Architectures: A Comparative Study.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

A Critical Assessment of DRAM-PIM Architectures - Trends, Challenges and Solutions.

[BibT_eX]

[DOI]

Lukas Steiner

Christian Weis

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

A Framework for Formal Verification of DRAM Controllers.

[BibT_eX]

[DOI]

Proceedings of the 2022 International Symposium on Memory Systems, 2022

Optimization of DRAM based PIM Architecture for Energy-Efficient Deep Neural Network Training.

[BibT_eX]

[DOI]

Christian Weis

Syed Mohammad Asad Hassan Jafri

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Correction to: Efficient Hardware Architectures for 1D- and MD-LSTM Networks.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2021

A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2020

Efficient Hardware Architectures for 1D- and MD-LSTM Networks.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2020

Efficient Generation of Application Specific Memory Controllers.

[BibT_eX]

[DOI]

Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

Multi-Valued Physical Unclonable Functions based on Dynamic Random Access Memory.

[BibT_eX]

[DOI]

Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

A Low Power In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions.

[BibT_eX]

[DOI]

Muhammad Mohsin Ghaffar

Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

2019

eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex.

[BibT_eX]

[DOI]

CoRR, 2019

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Channel Models for Physical Unclonable Functions based on DRAM Retention Measurements.

[BibT_eX]

[DOI]

Proceedings of the XVI International Symposium "Problems of Redundancy in Information and Control Systems", 2019

Fast validation of DRAM protocols with timed petri nets.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2019

An In-DRAM Neural Network Processing Engine.

[BibT_eX]

[DOI]