Chio-In Ieong
According to our database1,
Chio-In Ieong
authored at least 10 papers
between 2012 and 2024.
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Bibliography
2024
CoRR, 2024
The Impact of Transient and Stable Patterns of Functional Connectivity in Emotion Recognition.
Proceedings of the IEEE International Conference on Computational Intelligence and Virtual Environments for Measurement Systems and Applications, 2024
2019
A 0.12-mm<sup>2</sup> 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-µs Settling Time for Multi-ISM-Band ULP Radios.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2017
A 0.45 V 147-375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2017
2016
Wide Input Range Supply Voltage Tolerant Capacitive Sensor Readout Using On-Chip Solar Cell.
J. Circuits Syst. Comput., 2016
Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Sub-µW QRS detection processor using quadratic spline wavelet transform and maxima modulus pair recognition for power-efficient wireless arrhythmia monitoring.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Energy Optimized Subthreshold VLSI Logic Family With Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2015
2013
Sub-threshold standard cell library design for ultra-low power biomedical applications.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
2012
A 0.83-µW QRS Detection Processor Using Quadratic Spline Wavelet Transform for Wireless ECG Acquisition in 0.35-µm CMOS.
IEEE Trans. Biomed. Circuits Syst., 2012