Ching-Yuan Yeh

According to our database, Ching-Yuan Yeh authored at least 2 papers in 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2012

A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance.

Yu-Huei Lee, Shen-Yu Peng, Alex Chun-Hsien Wu, Chao-Chang Chiu, Yao-Yi Yang, Ming-Hsin Huang, Ke-Horng Chen, Ying-Hsi Lin, Shih-Wei Wang, Ching-Yuan Yeh, Chen-Chih Huang, Chao-Cheng Lee

Proceedings of the Symposium on VLSI Circuits, 2012

A single-inductor dual-output (SIDO) based power management with adaptive bus voltage modulation and zero cross-regulation in 40nm CMOS.

Yu-Huei Lee, Tzu-Chi Huang, Kuan-Yu Chu, Chao-Chang Chiu, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Ching-Yuan Yeh, Chen-Chih Huang, Chao-Cheng Lee

Proceedings of the 38th European Solid-State Circuit conference, 2012