Ching-Yuan Yang
Orcid: 0000-0002-5335-3665
According to our database1,
Ching-Yuan Yang
authored at least 56 papers
between 1998 and 2023.
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Bibliography
2023
A 30-GHz Frequency Doubler Using a Current Folding Technique in 90-nm CMOS Technology.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Behavior Simulation of CDR for SSC System With a Compact Quarter-Rate Linear Phase Detector.
Proceedings of the 20th International SoC Design Conference, 2023
2022
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
Proceedings of the 19th International SoC Design Conference, 2022
2021
A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links.
IEEE Trans. Very Large Scale Integr. Syst., 2021
A Self Synchronized-Switch Rectifier for Piezoelectric-Vibration Energy-Harvesting Systems.
Proceedings of the 18th International SoC Design Conference, 2021
A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
Proceedings of the International SoC Design Conference, 2020
Proceedings of the European Conference on Circuit Theory and Design, 2020
2019
A 10-GHz Fast-Locked All-Digital Frequency Synthesizer with Frequency-Error Detection.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
A Spur-Suppression Technique for Frequency Synthesizer with Pulse-Width to Current Conversion.
Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
Proceedings of the Advances in Artificial Intelligence, Software and Systems Engineering, 2019
2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
A 1.5-Gb/s adaptive equalizer with periodically embedded clock encoding for intra-panel interfaces.
Proceedings of the International SoC Design Conference, 2017
Proceedings of the International SoC Design Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A 90-nm CMOS Frequency Synthesizer with a Tripler for 60-GHz Wireless Communication Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
2015
A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Proceedings of the ESSCIRC 2013, 2013
2012
Proceedings of the International Symposium on Communications and Information Technologies, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0.35- μ m SiGe BiCMOS.
IEEE J. Solid State Circuits, 2011
A low-power direct digital frequency synthesizer using an analogue-sine-conversion technique.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
A Delta-Sigma PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
2008
IEEE Trans. Instrum. Meas., 2008
IEEE Trans. Ind. Electron., 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Injection-Locked Clock Recovery Using a Multiplexed Oscillator for Half-Rate Data-Recovered Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
A 2.5Gb/s oversampling clock and data recovery circuit with frequency calibration technique.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation.
IEICE Trans. Electron., 2007
A Fast-Locking Agile Frequency Synthesizer for MIMO Dual-mode WiFi / WiMAX Applications.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
High-Frequency Low-Noise Voltage-Controlled <i>LC</i>-Tank Oscillators Using a Tunable Inductor Technique.
IEICE Trans. Electron., 2006
IEICE Trans. Electron., 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A frequency synthesizer realized by a transformer-based voltage-controlled oscillator for IEEE 802.11a/b/g channels.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2002
IEEE J. Solid State Circuits, 2002
2001
A one-wire approach for skew-compensating clock distribution based on bidirectional techniques.
IEEE J. Solid State Circuits, 2001
2000
IEEE J. Solid State Circuits, 2000
IEEE J. Solid State Circuits, 2000
1998
IEEE J. Solid State Circuits, 1998