Ching-Yeh Chen
Orcid: 0000-0003-4952-3024
According to our database1,
Ching-Yeh Chen
authored at least 32 papers
between 2002 and 2024.
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Bibliography
2024
Evaluation of Low Complexity Enhancement Video Codec (LCEVC) with HEVC and VVC on 4K Content.
Proceedings of the Picture Coding Symposium, 2024
2021
2020
A VVC Proposal With Quaternary Tree Plus Binary-Ternary Tree Coding Block Structure and Advanced Coding Techniques.
IEEE Trans. Circuits Syst. Video Technol., 2020
2013
2012
IEEE Trans. Circuits Syst. Video Technol., 2012
2011
One-pass encoding algorithm for adaptive loop filter in high-efficiency video coding.
Proceedings of the 2011 IEEE Visual Communications and Image Processing, 2011
Proceedings of the IEEE 13th International Workshop on Multimedia Signal Processing (MMSP 2011), 2011
2008
J. Signal Process. Syst., 2008
Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine.
IEEE Trans. Circuits Syst. Video Technol., 2008
2007
On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.
IEEE Trans. Circuits Syst. Video Technol., 2007
Proceedings of the Visual Communications and Image Processing 2007, 2007
2006
Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results.
J. VLSI Signal Process., 2006
System Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering.
IEEE Trans. Signal Process., 2006
IEEE Trans. Multim., 2006
IEEE Trans. Circuits Syst. Video Technol., 2006
IEEE Trans. Circuits Syst. Video Technol., 2006
Analysis and architecture design of variable block-size motion estimation for H.264/AVC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
Analysis and VLSI architecture of update step in motion-compensated temporal filtering.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006
2005
IEEE Trans. Circuits Syst. Video Technol., 2005
Hardware architecture design of video compression for multimedia communication systems.
IEEE Commun. Mag., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 International Conference on Image Processing, 2005
Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering [video coding applications].
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
2004
Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Analysis and hardware architecture for global motion estimation in MPEG-4 Advanced Simple Profile.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003
Motion compensated de-interlacing with adaptive global motion estimation and compensation.
Proceedings of the 2003 International Conference on Image Processing, 2003
2002
Multiple sprites and frame skipping techniques for sprite generation with high subjective quality and fast speed.
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002
A fast and high subjective quality sprite generation algorithm with frame skipping and multiple sprites techniques.
Proceedings of the 2002 International Conference on Image Processing, 2002