Ching-Wei Wu

According to our database, Ching-Wei Wu authored at least 6 papers between 2004 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications.

Jonathan Chang, Yen-Huei Chen, Gary Chan, Kuo-Cheng Lin, Po-Sheng Wang, Yangsyu Lin, Sevic Chen, Peijiun Lin, Ching-Wei Wu, Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, Atul Katoch, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2017

12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications.

Michael Clinton, Hank Cheng, Hung-Jen Liao, Robin Lee, Ching-Wei Wu, Johnny Yang, Hau-Tai Hsieh, Frank Wu, Jung-Ping Yang, Atul Katoch, Arun Achyuthan, Donald Mikan, Bryan Sheffield, Jonathan Chang

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications.

Yen-Huei Chen, Kao-Cheng Lin, Ching-Wei Wu, Wei-Min Chan, Jhon-Jhy Liaw, Hung-Jen Liao, Jonathan Chang

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2014

Study of Scraping guide Ways Inspection.

Ching-Wei Wu, Ying-Shing Shiao, Ching-Feng Chang

J. Comput., 2014

A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS.

Ching-Wei Wu, Ming-Hung Chang, Chia-Cheng Chen, Robin Lee, Hung-Jen Liao, Jonathan Chang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2004

Failure Factor Based Yield Enhancement for SRAM Designs.

Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004