Ching-Che Chung
Orcid: 0000-0003-1398-4320
According to our database1,
Ching-Che Chung
authored at least 60 papers
between 2003 and 2024.
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
On csauthors.net:
Bibliography
2024
Implementation of Lightweight Convolutional Neural Networks with an Early Exit Mechanism Utilizing 40 nm CMOS Process for Fire Detection in Unmanned Aerial Vehicles.
Sensors, April, 2024
IEEE Trans. Instrum. Meas., 2024
2023
A Multiplier-Free Convolution Neural Network Hardware Accelerator for Real-Time Bearing Condition Detection of CNC Machinery.
Sensors, December, 2023
Lightweight CNN hardware accelerator using the ternary quantization method for fault diagnosis of CNC machinery.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023
2022
A Maximum Logarithmic Maximum a Posteriori Probability Based Soft-Input Soft-Output Detector for the Coded Spatial Modulation Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Body Channel Communication Transceiver with a 16x Oversampling CDR and Convolutional Codes.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
2020
Microelectron. J., 2020
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020
2019
A fast phase tracking reference-less all-digital CDR circuit for human body channel communication.
Microelectron. J., 2019
An All-Digital Temperature Sensor with Process and Voltage Variation Tolerance for IoT Applications.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019
2017
Microelectron. J., 2017
Turkish J. Electr. Eng. Comput. Sci., 2017
Turkish J. Electr. Eng. Comput. Sci., 2017
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEICE Electron. Express, 2016
Proceedings of the IEEE Sensors Applications Symposium, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the VLSI Design, Automation and Test, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Partial Parity Cache and Data Cache Management Method to Improve the Performance of an SSD-Based RAID.
IEEE Trans. Very Large Scale Integr. Syst., 2014
High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applications.
IEICE Electron. Express, 2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
An all-digital on-chip abnormal temperature warning sensor for dynamic thermal management.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
2013
A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65nm CMOS.
IEICE Electron. Express, 2013
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
An all-digital on-chip silicon oscillator with automatic VT range selection relative modeling.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A high-resolution and one-cycle conversion time-to-digital converter architecture for PET image applications.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
IEICE Electron. Express, 2012
A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technology.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
A low-complexity high-performance wear-leveling algorithm for flash memory system design.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
A 90 nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications.
J. Signal Process. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Built-in Self-Calibration Circuit for Monotonic Digitally Controlled Oscillator Design in 65-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS Technology.
IEEE J. Solid State Circuits, 2011
A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology.
IEICE Electron. Express, 2011
IEICE Electron. Express, 2011
2010
Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications.
IEICE Electron. Express, 2010
An all-digital smart temperature sensor with auto-calibration in 65nm CMOS technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
An all digital spread spectrum clock generator with programmable spread ratio for SoC applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2007
An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems.
Proceedings of the 2007 IEEE International SOC Conference, 2007
A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications.
IEEE J. Solid State Circuits, 2006
Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
IEEE Trans. Circuits Syst. II Express Briefs, 2005
An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
IEEE J. Solid State Circuits, 2004
2003
IEEE J. Solid State Circuits, 2003