Chin-Yang Wu

According to our database, Chin-Yang Wu authored at least 4 papers between 2014 and 2018.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2018

A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS.

Ting-Kuei Kuan, Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017

A 0.031mm², 910fs, 0.5-4GHz injection type SOC PLL with 90dB built-in supply noise rejection in 10nm FinFET CMOS.

Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2015

4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology.

Ping-Chuan Chiang, Jhih-Yu Jiang, Hao-Wei Hung, Chin-Yang Wu, Gaun-Sing Chen, Jri Lee

IEEE J. Solid State Circuits, 2015

2014

Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology.

Guan-Sing Chen, Chin-Yang Wu, Chen-Lun Lin, Hao-Wei Hung, Jri Lee

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014