Chin-Yang Lo
According to our database1,
Chin-Yang Lo
authored at least 3 papers
between 2019 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
2019
2020
2021
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Bibliography
2021
Energy-Efficient Accelerator Design With Tile-Based Row-Independent Compressed Memory for Sparse Compressed Convolutional Neural Networks.
IEEE Open J. Circuits Syst., 2021
2020
Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
An Energy-Efficient Accelerator with Relative- Indexing Memory for Sparse Compressed Convolutional Neural Network.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019