Chin-Hua Wen

According to our database1, Chin-Hua Wen authored at least 4 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

2010
2012
2014
2016
2018
2020
2022
2024
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1
2
1
1
1
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Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A 0.296pJ/bit 17.9Tb/s/mm<sup>2</sup> Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2020
A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2016
A sub-micron CMOS-based ISFET array for biomolecular sensing.
Proceedings of the 11th IEEE Annual International Conference on Nano/Micro Engineered and Molecular Systems, 2016

2010
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010


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