Chihun Lee

According to our database¹, Chihun Lee authored at least 9 papers between 2006 and 2020.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2020

Scalable and High-Throughput Top-Down Manufacturing of Optical Metasurfaces.

[BibT_eX]

[DOI]

Sensors, 2020

Development of Artificial Neural Network System to Recommend Process Conditions of Injection Molding for Various Geometries.

[BibT_eX]

[DOI]

Adv. Intell. Syst., 2020

2012

A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2009

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

2008

A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

2007

A 1.2-V 37-38.5-GHz Eight-Phase Clock Generator in 0.13-µm CMOS Technology.

[BibT_eX]

[DOI]

Lan-Chou Cho

Chihun Lee

Shen-Iuan Liu

IEEE J. Solid State Circuits, 2007

A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS.

[BibT_eX]

[DOI]

Chihun Lee

Shen-Iuan Liu

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS.

[BibT_eX]

[DOI]

Lan-Chou Cho

Chihun Lee

Shen-Iuan Liu

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology.

[BibT_eX]

[DOI]

Chihun Lee

Lan-chou Cho

Shen-Iuan Liu

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Chihun Lee

Timeline

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