Chiharu Tsuruta

According to our database, Chiharu Tsuruta authored at least 6 papers between 2015 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2017

Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled Accelerators.

Takahiro Kaneda, Ryotaro Sakai, Naoki Nishikawa, Toshihiro Hanawa, Chiharu Tsuruta, Hideharu Amano

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA.

Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

Trax solver on Zynq using incremental update algorithm.

Hiroshi Nakahara, Tetsui Ohkubo, Hideki Shimura, Ryotaro Sakai, Chiharu Tsuruta, Takahiro Kaneda, Hideharu Amano

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015

Off-Loading LET Generation to PEACH2: A Switching Hub for High Performance GPU Clusters.

Chiharu Tsuruta, Yohei Miki, Takuya Kuhara, Hideharu Amano, Masayuki Umemura

SIGARCH Comput. Archit. News, 2015

Trax solver on Zynq with Deep Q-Network.

Naru Sugimoto, Takuji Mitsuishi, Takahiro Kaneda, Chiharu Tsuruta, Ryotaro Sakai, Hideki Shimura, Hideharu Amano

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Reduction calculator in an FPGA based switching Hub for high performance clusters.

Takuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa, Hideharu Amano

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015