Chih-Wen Yang

According to our database, Chih-Wen Yang authored at least 6 papers between 2014 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2022

Clock Design Methodology for Energy and Computation Efficient Bitcoin Mining Machines.

Chien-Pang Lu, Iris Hui-Ru Jiang, Chih-Wen Yang

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2020

Late Breaking Results: Design Dependent Mega Cell Methodology for Area and Power Optimization.

Chien-Pang Lu, Iris Hui-Ru Jiang, Chih-Wen Yang

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2016

A 2.6mm² 0.19nJ/pixel VP9 and multi-standard decoder LSI for Android 4K TV applications.

Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Chia-Yun Cheng, Hue-Min Lin, Chun-Chia Chen, Min-Hao Chiu, Ping Chao, Ming-Long Wu, Meng-Jye Hu, Sheng-Jen Wang, Che-Hong Chen, Shun-Hsiang Chuang, Hsiu-Yi Lin, Fu-Chun Yeh, Chia-Hung Kao, Yi-Chang Chen, Chia-Lin Ho, Yenchieh Huang, Hsiao-En Chen, Chih-Wen Yang, Hsuan-Wen Peng

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

2015

An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes.

Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee

IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications.

Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee

Proceedings of the ESSCIRC Conference 2015, 2015

2014

Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes.

Chih-Wen Yang, Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014