Chih-Wei Yao
Orcid: 0000-0002-6818-0955
According to our database1,
Chih-Wei Yao
authored at least 17 papers
between 1996 and 2022.
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Bibliography
2022
A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO.
IEEE J. Solid State Circuits, 2021
32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2019
A 28-nm 75-fs<sub>rms</sub> Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction.
IEEE J. Solid State Circuits, 2019
A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2019
A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2017
A 14-nm 0.14-ps<sub>rms</sub> Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration.
IEEE J. Solid State Circuits, 2017
24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2013
A 2.8-3.2-GHz Fractional- N Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO.
IEEE J. Solid State Circuits, 2013
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Frequency Synthesis with Arbitrary Input Clock Rate and Rational K/L Multiplier Ratio.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
A programmable 25 MHz to 6 GHz rational-K/L frequency synthesizer with digital Kvco compensation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2006
A phase-noise reduction technique for quadrature LC-VCO with phase-to-amplitude noise conversion.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
1996
Pattern classification approach to characterizing solitary pulmonary nodules imaged on high-resolution computed tomography.
Proceedings of the Medical Imaging 1996: Image Processing, 1996