Chih-Wea Wang

According to our database¹, Chih-Wea Wang authored at least 16 papers between 2000 and 2017.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2017

Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2012

Test for more than pass/fail using on-chip temperature sensor.

[BibT_eX]

[DOI]

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2007

STEAC: A Platform for Automatic SOC Test Integration.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

2004

An SOC Test Integration Platform and Its Industrial Realization.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Failure Factor Based Yield Enhancement for SRAM Designs.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003

Test and Diagnosis of Word-Oriented Multiport Memories.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Fault Pattern Oriented Defect Diagnosis for Memories.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

FAME: A Fault-Pattern Based Memory Failure Analysis Framework.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Test Scheduling of BISTed Memory Cores for SOC.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Test Scheduling and Test Access Architecture Optimization for System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Error Catch and Analysis for Semiconductor Memories Using March Tests.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

A built-in self-test and self-diagnosis scheme for embedded SRAM.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Chih-Wea Wang

Timeline

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