Chih-Tsun Huang

Orcid: 0000-0002-0214-6826

According to our database¹, Chih-Tsun Huang authored at least 72 papers between 1997 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

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In proceedings

Article

PhD thesis

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Links

On csauthors.net:

Bibliography

2024

BEACON: Block-wise Efficient Architecture Co-optimization for DNN-HW-Mapping with Zero-cost Evaluation and Progressive Distillation.

[BibT_eX]

[DOI]

Jiun-Kai Yang

Yao-Hua Chen

Chih-Tsun Huang

Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

2023

HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Efficient Hand Gesture Recognition using Multi-Task Multi-Modal Learning and Self-Distillation.

[BibT_eX]

[DOI]

Proceedings of the ACM Multimedia Asia 2023, 2023

Optimization of AI SoC with Compiler-assisted Virtual Design Platform.

[BibT_eX]

[DOI]

Proceedings of the 2023 International Symposium on Physical Design, 2023

MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE International Conference on Computer Design, 2023

2022

Efficient Segment-wise Pruning for DCNN Inference Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

Fast DNN-based Mechatronics Prototyping Platform on Robotic Arm Control.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

Design and Optimization of a Pruning-Efficient DCNN Inference Accelerator.

[BibT_eX]

[DOI]

Che-Hao Chang

Chih-Tsun Huang

Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2019

Efficient Dynamic Fixed-Point Quantization of CNN Inference Accelerators for Edge Devices.

[BibT_eX]

[DOI]

Yueh-Chi Wu

Chih-Tsun Huang

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

Data Locality Optimization of Depthwise Separable Convolutions for CNN Inference Accelerators.

[BibT_eX]

[DOI]

Hao-Ning Wu

Chih-Tsun Huang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2017

Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Design space exploration with a cycle-accurate systemC/TLM DRAM controller model.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2016

IoT: Source of test challenges.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE European Test Symposium, 2016

2015

Application-level embedded communication tracer for many-core systems.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Design of a scalable many-core processor for embedded applications.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Design of low-cost elliptic curve cryptographic engines for ubiquitous security.

[BibT_eX]

[DOI]

Hsin-Yu Ting

Chih-Tsun Huang

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

2013

AC-Plus Scan Methodology for Small Delay Testing and Characterization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Design of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures.

[BibT_eX]

[DOI]

Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

2012

Design and analysis of a many-core processor architecture for multimedia applications.

[BibT_eX]

[DOI]

Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2012

2011

Energy-Adaptive Dual-Field Processor for High-Performance Elliptic Curve Cryptographic Applications.

[BibT_eX]

[DOI]

Jyu-Yuan Lai

Chih-Tsun Huang

IEEE Trans. Very Large Scale Integr. Syst., 2011

Hardware/software co-designed accelerator for vector graphics applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

Reliability analysis and improvement for multi-level non-volatile memories with soft information.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Single- and Multi-core Configurable AES Architectures for Flexible Security.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

High-performance architecture for Elliptic Curve Cryptography over binary field.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009

A Highly Efficient Cipher Processor for Dual-Field Elliptic Curve Cryptography.

[BibT_eX]

[DOI]

Jyu-Yuan Lai

Chih-Tsun Huang

IEEE Trans. Circuits Syst. II Express Briefs, 2009

2008

Elixir: High-Throughput Cost-Effective Dual-Field Processors and the Design Framework for Elliptic Curve Cryptography.

[BibT_eX]

[DOI]

Jyu-Yuan Lai

Chih-Tsun Huang

IEEE Trans. Very Large Scale Integr. Syst., 2008

An embedded infrastructure of debug and trace interface for the DSP platform.

[BibT_eX]

[DOI]

Ming-Chang Hsieh

Chih-Tsun Huang

Proceedings of the 45th Design Automation Conference, 2008

Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Optimization of Pattern Matching Circuits for Regular Expression on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

BIST-based diagnosis scheme for field programmable gate array interconnect delay faults.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

A prototype of a wireless-based test system.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International SOC Conference, 2007

A High-Throughput Low-Power AES Cipher for Network Applications.

[BibT_eX]

[DOI]

Shin-Yi Lin

Chih-Tsun Huang

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Optimization of regular expression pattern matching circuits on FPGA.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

A network security processor design based on an integrated SOC design and test platform.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

A BIST Scheme for FPGA Interconnect Delay Faults.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A systematic approach to reducing semiconductor memory test time in mass production.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Design and test of a scalable security processor.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A configurable AES processor for enhanced security.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

An SOC Test Integration Platform and Its Industrial Realization.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

An Application-Independent Delay Testing Methodology for Island-Style FPGA.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Failure Factor Based Yield Enhancement for SRAM Designs.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

On Test and Diagnostics of Flash Memories.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

An HMAC processor with integrated SHA-1 and MD5 algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Built-in redundancy analysis for memory yield improvement.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2003

A high-throughput low-cost AES processor.

[BibT_eX]

[DOI]

IEEE Commun. Mag., 2003

Test and Diagnosis of Word-Oriented Multiport Memories.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Fault Pattern Oriented Defect Diagnosis for Memories.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

FAME: A Fault-Pattern Based Memory Failure Analysis Framework.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Design of a scalable RSA and ECC crypto-processor.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

A highly efficient AES cipher chip.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Fault simulation and test algorithm generation for random accessmemories.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Diagonal Test and Diagnostic Schemes for Flash Memorie.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Flash Memory Built-In Self-Test Using March-Like Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Test Scheduling of BISTed Memory Cores for SOC.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Test Scheduling and Test Access Architecture Optimization for System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

March-based RAM diagnosis algorithms for stuck-at and coupling faults.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Simulation-Based Test Algorithm Generation for Random Access Memories.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Error Catch and Analysis for Semiconductor Memories Using March Tests.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

BRAINS: A BIST Compiler for Embedded Memories.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

A programmable built-in self-test core for embedded memories.

[BibT_eX]

[DOI]

Chih-Tsun Huang

Jing-Reng Huang

Cheng-Wen Wu

Proceedings of ASP-DAC 2000, 2000

1999

A Programmable BIST Core for Embedded DRAM.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1999

RAMSES: A Fast Memory Fault Simulator.

[BibT_eX]

[DOI]

Chi-Feng Wu

Chih-Tsun Huang

Cheng-Wen Wu

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1997

High-speed C-testable systolic array design for Galois-field inversion.

[BibT_eX]

[DOI]

Chih-Tsun Huang

Cheng-Wen Wu

Proceedings of the European Design and Test Conference, 1997

Chih-Tsun Huang

Timeline

Legend:

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On csauthors.net:

Bibliography

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