Chih-Pin Su

According to our database¹, Chih-Pin Su authored at least 10 papers between 2002 and 2010.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of five.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2010

Single- and Multi-core Configurable AES Architectures for Flexible Security.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

2005

Design and test of a scalable security processor.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A configurable AES processor for enhanced security.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A Graph-Based Approach to Power-Constrained SOC Test Scheduling.

[BibT_eX]

[DOI]

Chih-Pin Su

Cheng-Wen Wu

J. Electron. Test., 2004

An HMAC processor with integrated SHA-1 and MD5 algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

A high-throughput low-cost AES processor.

[BibT_eX]

[DOI]

IEEE Commun. Mag., 2003

Design of a scalable RSA and ECC crypto-processor.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

A highly efficient AES cipher chip.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

A Hierarchical Test Methodology for Systems on Chip.

[BibT_eX]

[DOI]

IEEE Micro, 2002

A Hierarchical Test Scheme for System-On-Chip Designs.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Chih-Pin Su

Timeline

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Links

On csauthors.net:

Bibliography

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