Chih-Mou Tseng

According to our database, Chih-Mou Tseng authored at least 4 papers between 2009 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

Test clock domain optimization for peak power supply noise reduction during scan.

Jen-Yang Wen, Yu-Chuan Huang, Min-Hong Tsai, Kuan-Yu Liao, James Chien-Mo Li, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li

Proceedings of the 2011 IEEE International Test Conference, 2011

2010

Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs.

Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia-Tso Chao, Shi-Hao Chen, Chih-Mou Tseng, Tsung-Ying Tsai

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

TSV redundancy: Architecture and design issues in 3D IC.

Ang-Chih Hsieh, TingTing Hwang, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li

Proceedings of the Design, Automation and Test in Europe, 2010

2009

BIST design optimization for large-scale embedded memory cores.

Tzuo-Fan Chien, Wen-Chi Chao, James Chien-Mo Li, Yao-Wen Chang, Kuan-Yu Liao, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009