Chih-Ming Hung

Orcid: 0009-0005-6613-5834

According to our database1, Chih-Ming Hung authored at least 29 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
Semiconductor Chip Design in a Legoland.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2019

2018
F4: Circuit and system techniques for mm-wave multi-antenna systems.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2017

2016
F3: Radio architectures and circuits towards 5G.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Recent research development and new challenges in analog layout synthesis.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2014
A fully integrated translational tracking filter with >40dB blocker attenuation and >68dB harmonic rejection in 40nm for Digital TV tuner applications.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
An adaptive predistorter for wireless LAN RFSoC with embedded PA and T/R switch in 55nm CMOS.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2011
Spur-free all-digital PLL in 65nm for mobile phones.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A 0.8mm<sup>2</sup> all-digital SAW-less polar transmitter in 65nm EDGE SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Towards terahertz operation of CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

A 410GHz CMOS Push-Push Oscillator with an On-Chip Patch Antenna.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006
LMS-based calibration of an RF digitally controlled oscillator for mobile phones.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process.
IEEE J. Solid State Circuits, 2006

A digitally controlled oscillator system for SAW-less transmitters in cellular handsets.
IEEE J. Solid State Circuits, 2006

Charge-Domain Signal Processing of Direct RF Sampling Mixer with Discrete-Time Filters in Bluetooth and GSM Receivers.
EURASIP J. Wirel. Commun. Netw., 2006


2005
SoC with an integrated DSP and a 2.4-GHz RF transmitter.
IEEE Trans. Very Large Scale Integr. Syst., 2005

All-digital PLL and transmitter for mobile phones.
IEEE J. Solid State Circuits, 2005

A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones.
IEEE J. Solid State Circuits, 2005

Sigma-Delta Noise Shaping for Digital-to-Frequency and Digital-to-RF-Amplitude Conversion.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005



2004
All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS.
IEEE J. Solid State Circuits, 2004

2002
A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop.
IEEE J. Solid State Circuits, 2002

Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters.
IEEE J. Solid State Circuits, 2002

Wireless interconnects for clock distribution.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

2000
A packaged 1.1-GHz CMOS VCO with phase noise of -126 dBc/Hz at a 600-kHz offset.
IEEE J. Solid State Circuits, 2000


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