Chih-Lung Chen

Orcid: 0000-0001-6059-9869

According to our database¹, Chih-Lung Chen authored at least 28 papers between 2008 and 2022.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2022

CoNN-IDS: Intrusion detection system based on collaborative neural networks and agile training.

[BibT_eX]

[DOI]

Comput. Secur., 2022

2021

A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Preserving indomitable DDoS vitality through resurrection social hybrid botnet.

[BibT_eX]

[DOI]

Comput. Secur., 2021

2020

Towards Accurate and Efficient Classification of Power System Contingencies and Cyber-Attacks Using Recurrent Neural Networks.

[BibT_eX]

[DOI]

IEEE Access, 2020

2016

A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory.

[BibT_eX]

[DOI]

Kin-Chu Ho

Chih-Lung Chen

Hsie-Chia Chang

IEEE Trans. Very Large Scale Integr. Syst., 2016

An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC Conference 2015, 2015

2014

A 7.11mJ/Gb/query data-driven machine learning processor (D<sup>2</sup>MLP) for big data analysis and applications.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2014

Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013

Integrating Non-Repetitive LT Encoders With Modified Distribution to Achieve Unequal Erasure Protection.

[BibT_eX]

[DOI]

IEEE Trans. Multim., 2013

Modified Robust Soliton Distribution (MRSD) with Improved Ripple Size for LT Codes.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2013

An Iterative Weighted Reliability Decoding Algorithm for Two-Step Majority-Logic Decodable Cyclic Codes.

[BibT_eX]

[DOI]

Hsiu-Chi Chang

Chih-Lung Chen

Hsie-Chia Chang

IEEE Commun. Lett., 2013

Adjusted robust Soliton distribution (ARSD) with reshaped ripple size for LT codes.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Wireless Communications and Signal Processing, 2013

2012

A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

An improved LT encoding scheme with extended chain lengths.

[BibT_eX]

[DOI]

Kuo-Kuang Yen

Chih-Lung Chen

Hsie-Chia Chang

Proceedings of the International Symposium on Information Theory and its Applications, 2012

Stochastic decoding for LDPC convolutional codes.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Non-repetitive encoding with increased degree-1 encoding symbols for LT codes.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2010

A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

2009

Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 11.5-Gbps LDPC decoder based on CP-PEG code construction.

[BibT_eX]

[DOI]

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008

An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

Chih-Lung Chen

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