Chih-Kong Ken Yang

Orcid: 0000-0002-2993-7724

According to our database1, Chih-Kong Ken Yang authored at least 91 papers between 1996 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2011, "For leadership in enhancement of input-output efficiency in integrated circuits".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2024
Invited Paper: A Pseudo-Differential Architecture for Low-Power Voltage-to-Time Converters.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Cryogenic Alternative: CMOS Versus Dynamic-Based Logic.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

2022
A Scalable 20V Charge-Pump-Based Driver in 65nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Pulsed-Coherent Lidar With Sub-10 μm Precision.
IEEE J. Solid State Circuits, 2022

A 14-bit 1-GS/s SiGe Bootstrap Sampler for High Resolution ADC with 250-MHz Input.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS.
Proceedings of the 47th ESSCIRC 2021, 2021

A 6μm-Precision Pulsed-Coherent Lidar with a 40-dB Tuning Range Inverter-Based Phase-Invariant PGA.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
A Class-D FVF LDO With Multi-Level PWM Gate Control, 280-ns Settling Time, and No Overshoot/Undershoot.
IEEE Trans. Circuits Syst., 2020

A 92%-Efficiency Battery Powered Hybrid DC-DC Converter for IoT Applications.
IEEE Trans. Circuits Syst., 2020

2019
An 85%-Efficiency Hybrid DC-DC Converter for Sub-Microwatt IoT Applications.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

An 8.5pJ/bit Ultra-Low Power Wake-Up Receiver Using Schottky Diodes for IoT Applications.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 19-GHz Pulsed-Coherent ToF Receiver With 40-μm Precision for Laser Ranging Systems.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2017
A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology.
IEEE J. Solid State Circuits, 2017

2015
A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A 32-48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015

A 50-64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015

A low-PDP and low-area repeater using passive CTLE for on-chip interconnects.
Proceedings of the Symposium on VLSI Circuits, 2015

Effects of Active Cooling on Workload Management in High Performance Processors.
Proceedings of the CLOSER 2015, 2015

2014
Stability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Flexible-Assignment Calibration Technique for Mismatch-Constrained Digital-to-Analog Converters.
IEEE Trans. Very Large Scale Integr. Syst., 2014

23.8 A 34V charge pump in 65nm bulk CMOS technology.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A compact stacked-device output driver in low-voltage CMOS Technology.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 50-64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A 12-V charge pump-based square wave driver in 65-nm CMOS technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
Effects of Using Advanced Cooling Systems on the Overall Power Consumption of Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

An INL Yield Model of the Digital-to-Analog Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Analysis and Design of Superharmonic Injection-Locked Multipath Ring Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

In Situ SRAM Static Stability Estimation in 65-nm CMOS.
IEEE J. Solid State Circuits, 2013

A 0.1-1.5 GHz 8-bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection.
IEEE J. Solid State Circuits, 2013

A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding.
IEEE J. Solid State Circuits, 2013

A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A bipolar >40-V driver in 45-nm SOI CMOS technology.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Nearly Exact Analytical Formulation of the DNL Yield of the Digital-to-Analog Converter.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Power Optimized ADC-Based Serial Link Receiver.
IEEE J. Solid State Circuits, 2012

A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding.
Proceedings of the Symposium on VLSI Circuits, 2012

A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs).
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

A low-power highly multiplexed parallel PRBS generator.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Multilevel Power Optimization of Pipelined A/D Converters.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Design and Optimization of Multipath Ring Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Analysis of STT-RAM cell design with multiple MTJs per access.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Scalability and design-space analysis of a 1T-1MTJ memory cell.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

A 4.6GHz MDLL with -46dBc reference spur and aperture position tuning.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
Guest Editorial for Special Issue on High-Performance Multichip Interconnections.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

ADC-Based Serial I/O Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Convex Piecewise-Linear Modeling Method for Circuit Optimization via Geometric Programming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A Phase-Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology.
IEEE J. Solid State Circuits, 2010

Clocking Links in Multi-chip Packages: A Case Study.
Proceedings of the IEEE 18th Annual Symposium on High Performance Interconnects, 2010

2009
A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization.
IEEE J. Solid State Circuits, 2009

An LC-Based Clock Buffer With Tunable Injection Locking.
IEEE J. Solid State Circuits, 2009

Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages.
IEEE J. Solid State Circuits, 2009

A stochastic jitter model for analyzing digital timing-recovery circuits.
Proceedings of the 46th Design Automation Conference, 2009

A nonlinear phase detector for digital phase locked loops.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
A Comprehensive Delay Model for CMOS CML Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Edge and Data Adaptive Equalization of Serial-Link Transceivers.
IEEE J. Solid State Circuits, 2008

Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric.
IEEE J. Solid State Circuits, 2008

Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Technique to Reduce the Resolution Requirement of Digitally Controlled Oscillators for Digital PLLs.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions.
IEEE J. Solid State Circuits, 2007

A Large-Swing Transformer-Boosted Serial Link Transmitter With > V<sub>DD</sub> Swing.
IEEE J. Solid State Circuits, 2007

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE.
IEEE J. Solid State Circuits, 2007

An Adaptive Low-Jitter LC-Based Clock Distribution.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Device-circuit co-optimization for mixed-mode circuit design via geometric programming.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A Comprehensive Phase-Transfer Model for Delay-Locked Loops.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A Study of the Optimal Data Rate for Minimum Power of I/Os.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter.
IEEE J. Solid State Circuits, 2006

A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration.
IEEE J. Solid State Circuits, 2006

Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2006

A sub-10-ps multiphase sampling system using redundancy.
IEEE J. Solid State Circuits, 2006

A Serial-Link Transceiver with Transition Equalization.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

An 8Gb/s Transformer-Boosted Transmitter with >V<sub>00</sub> swing.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Power-centric design of high-speed I/Os.
Proceedings of the 43rd Design Automation Conference, 2006

2004
Offset compensation in comparators with minimum input-referred supply noise.
IEEE J. Solid State Circuits, 2004

A 27-mW 3.6-gb/s I/O transceiver.
IEEE J. Solid State Circuits, 2004

2003
Methodology for on-chip adaptive jitter minimization in phase-locked loops.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation.
IEEE J. Solid State Circuits, 2003

Analysis of timing recovery for multi-Gbps PAM transceivers.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

CMOS LC oscillator using variable mean frequency.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops.
IEEE J. Solid State Circuits, 2002

Jitter optimization based on phase-locked loop design parameters.
IEEE J. Solid State Circuits, 2002

2001
A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-μm CMOS.
IEEE J. Solid State Circuits, 2001

2000
A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver.
IEEE J. Solid State Circuits, 2000

1999
A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter.
IEEE J. Solid State Circuits, 1999

A 14-bit, 10-Msamples/s D/A converter using multibit ΣΔ modulation.
IEEE J. Solid State Circuits, 1999

1998
High-speed electrical signaling: overview and limitations.
IEEE Micro, 1998

A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling.
IEEE J. Solid State Circuits, 1998

1996
A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links.
IEEE J. Solid State Circuits, 1996


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