Chih-Kong Ken Yang
Orcid: 0000-0002-2993-7724
According to our database1,
Chih-Kong Ken Yang
authored at least 91 papers
between 1996 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2011, "For leadership in enhancement of input-output efficiency in integrated circuits".
Timeline
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On csauthors.net:
Bibliography
2024
Invited Paper: A Pseudo-Differential Architecture for Low-Power Voltage-to-Time Converters.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS.
Proceedings of the 47th ESSCIRC 2021, 2021
A 6μm-Precision Pulsed-Coherent Lidar with a 40-dB Tuning Range Inverter-Based Phase-Invariant PGA.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
A Class-D FVF LDO With Multi-Level PWM Gate Control, 280-ns Settling Time, and No Overshoot/Undershoot.
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst., 2020
2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
An 8.5pJ/bit Ultra-Low Power Wake-Up Receiver Using Schottky Diodes for IoT Applications.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 19-GHz Pulsed-Coherent ToF Receiver With 40-μm Precision for Laser Ranging Systems.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2017
IEEE J. Solid State Circuits, 2017
2015
A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A 32-48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015
A 50-64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the CLOSER 2015, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Flexible-Assignment Calibration Technique for Mismatch-Constrained Digital-to-Analog Converters.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A 50-64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
Effects of Using Advanced Cooling Systems on the Overall Power Consumption of Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE J. Solid State Circuits, 2013
A 0.1-1.5 GHz 8-bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection.
IEEE J. Solid State Circuits, 2013
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Nearly Exact Analytical Formulation of the DNL Yield of the Digital-to-Analog Converter.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Proceedings of the Symposium on VLSI Circuits, 2012
A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs).
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Convex Piecewise-Linear Modeling Method for Circuit Optimization via Geometric Programming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
A Phase-Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology.
IEEE J. Solid State Circuits, 2010
Proceedings of the IEEE 18th Annual Symposium on High Performance Interconnects, 2010
2009
IEEE J. Solid State Circuits, 2009
IEEE J. Solid State Circuits, 2009
Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages.
IEEE J. Solid State Circuits, 2009
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
Technique to Reduce the Resolution Requirement of Digitally Controlled Oscillators for Digital PLLs.
IEEE Trans. Circuits Syst. II Express Briefs, 2007
IEEE J. Solid State Circuits, 2007
A Large-Swing Transformer-Boosted Serial Link Transmitter With > V<sub>DD</sub> Swing.
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Device-circuit co-optimization for mixed-mode circuit design via geometric programming.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter.
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
2004
IEEE J. Solid State Circuits, 2004
2003
IEEE Trans. Circuits Syst. II Express Briefs, 2003
IEEE J. Solid State Circuits, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops.
IEEE J. Solid State Circuits, 2002
IEEE J. Solid State Circuits, 2002
2001
A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-μm CMOS.
IEEE J. Solid State Circuits, 2001
2000
IEEE J. Solid State Circuits, 2000
1999
IEEE J. Solid State Circuits, 1999
IEEE J. Solid State Circuits, 1999
1998
A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling.
IEEE J. Solid State Circuits, 1998
1996
IEEE J. Solid State Circuits, 1996