Chih-Chang Lin

According to our database, Chih-Chang Lin authored at least 18 papers between 1994 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Exploring User Engagement with Smartwatch Health Services: A Comparative Study Between Taiwan and Singapore.

Chih-Chang Lin, Fang-Wu Tung, Chien-Hsiung Chen

Proceedings of the Cross-Cultural Design, 2024

2020

Design Guidelines of Social-Assisted Robots for the Elderly: A Mixed Method Systematic Literature Review.

Chih-Chang Lin, Hao-Yu Liao, Fang-Wu Tung

Proceedings of the HCI International 2020 - Late Breaking Papers: Cognition, Learning and Games, 2020

2019

A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET.

Dirk Pfaff, Shahaboddin Moazzeni, Leisheng Gao, Mei-Chen Chuang, Xin-Jie Wang, Chai Palusa, Robert Abbott, Rolando Ramirez, Maher Amer, Ming-Chieh Huang, Chih-Chang Lin, Fred Kuo, Wei-Li Chen, Tae Young Goh, Kenny Hsieh

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET.

Dirk Pfaff, Robert Abbott, Xin-Jie Wang, Babak Zamanlooy, Shahaboddin Moazzeni, Raleigh Smith, Chih-Chang Lin

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2014

8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS.

Tsung-Ching Huang, Tao-Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Fu-Lung Hsueh

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012

A 2.7GHz 3.9mW Mesh-BJT LC-VCO with -204dBc/Hz FOM in 65nm CMOS.

Tao-Wen Chung, Tsung-Ching Huang, S. Chung, Ming-Chieh Huang, Chih-Chang Lin, Chan-Hong Chern, Fu-Lung Hsueh

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

1999

Logic synthesis for engineering change.

Chih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998

Cost-free scan: a low-overhead scan path design.

Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Test-point insertion: scan paths through functional logic.

Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs.

Peichen Pan, Chih-Chang Lin

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

1997

On designing universal logic blocks and their application to FPGA design.

Chih-Chang Lin, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1996

Sequential Permissible Functions and their Application to Circuit Optimization.

Chih-Chang Lin, Malgorzata Marek-Sadowska, Kuang-Chien Chen, Mike Tien-Chien Lee

Proceedings of the 1996 European Design and Test Conference, 1996

Test Point Insertion: Scan Paths through Combinational Logic.

Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee

Proceedings of the 33st Conference on Design Automation, 1996

1995

Cost-free scan: a low-overhead scan path design methodology.

Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Circuit partitioning with logic perturbation.

David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Logic Synthesis for Engineering Change.

Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng

Proceedings of the 32st Conference on Design Automation, 1995

Logic rectification and synthesis for engineering change.

Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

Universal logic gate for FPGA design.

Chih-Chang Lin, Malgorzata Marek-Sadowska, Duane Gatlin

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994