Chien-Ting Wu
According to our database1,
Chien-Ting Wu
authored at least 5 papers
between 2009 and 2024.
Collaborative distances:
Collaborative distances:
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2024
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Bibliography
2024
Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2015
Proceedings of the 10th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2015
2014
IEEE Trans. Intell. Transp. Syst., 2014
2009
Proceedings of the 33rd Annual IEEE International Computer Software and Applications Conference, 2009