Chien-Mo James Li

Proceedings of the IEEE European Test Symposium, 2024

Low-Complexity Algorithmic Test Generation for Neuromorphic Chips.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Diagnosis of Quantum Circuits in the NISQ Era.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Vmin Prediction Using Nondestructive Stress Test.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2023

Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2023

2022

ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2022

Diagnosing Double Faulty Chains through Failing Bit Separation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2022

Low-IR-Drop Test Pattern Regeneration Using A Fast Predictor.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Automatic Test Configuration and Pattern Generation (ATCPG) for Neuromorphic Chips.

[BibT_eX]

[DOI]

I-Wei Chiu

Xin-Ping Chen

Jennifer Shueh-Inn Hu

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Vector-based Dynamic IR-drop Prediction Using Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2021

Chip Performance Prediction Using Machine Learning Techniques.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2021

Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2021

Fault Modeling and Testing of Spiking Neural Network Chips.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2021

Machine Learning-Based Test Pattern Generation for Neuromorphic Chips.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020

qATG: Automatic Test Generation for Quantum Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

Diagnosis technique for Clustered Multiple Transition Delay Faults.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2020

Automatic IR-Drop ECO Using Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2020

High Efficiency and Low Overkill Testing for Probabilistic Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2020

Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Systematic Hold-time Fault Diagnosis and Failure Debug in Production Chips.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

ATPG and Test Compression for Probabilistic Circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

2018

A new method for parameter estimation of high-order polynomial-phase signals.

[BibT_eX]

[DOI]

Signal Process., 2018

IR drop prediction of ECO-revised circuits using machine learning.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Diagnosis and repair of cells (DRC) responsible for power-supply-noise violations.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on VLSI Design, 2018

Parallel order ATPG for test compaction.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on VLSI Design, 2018

Test methodology for PCHB/PCFB Asynchronous Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

Machine-learning-based dynamic IR drop prediction for ECO.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction.

[BibT_eX]

[DOI]

Jie-Hong Roland Jiang

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

PSN-aware circuit test timing prediction using machine learning.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2017

Robust test pattern generation for hold-time faults in nanometer technologies.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Physical-aware diagnosis of multiple interconnect defects.

[BibT_eX]

[DOI]

Proceedings of the International Test Conference in Asia, 2017

Test Methodology for Dual-rail Asynchronous Circuits.

[BibT_eX]

[DOI]

Kuan-Yen Huang

Ting-Yu Shen

Proceedings of the 54th Annual Design Automation Conference, 2017

Test Pattern Compression for Probabilistic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Test Pattern Modification for Average IR-Drop Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse.

[BibT_eX]

[DOI]

Hung-I Lee

Chen-Yo Han

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

2015

TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design, Automation and Test, 2015

Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

IEEE Trans. Very Large Scale Integr. Syst., 2014

Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Physical-aware systematic multiple defect diagnosis.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2014

Divide and conquer diagnosis for multiple defects.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

GPU-based timing-aware test generation for small delay defects.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

2013

Compact Test Pattern Selection for Small Delay Defect.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Automatic test pattern generation for delay defects using timed characteristic functions.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

GPU-based n-detect transition fault ATPG.

[BibT_eX]

[DOI]

Kuan-Yu Liao

Sheng-Chang Hsu

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Test Generation of Path Delay Faults Induced by Defects in Power TSV.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

Proceedings of the 22nd Asian Test Symposium, 2013

Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores.

[BibT_eX]

[DOI]

Geng-Ming Chiu

IEEE Trans. Very Large Scale Integr. Syst., 2012

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example.

[BibT_eX]

[DOI]

Yu-Shun Wang

Min-Han Hsieh

Charlie Chung-Ping Chen

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis.

[BibT_eX]

[DOI]

Wei-Lin Tsai

Wei-Chih Liu

IEEE Trans. Computers, 2012

3D IC test scheduling using simulated annealing.

[BibT_eX]

[DOI]

Chih-Yao Hsu

Chun-Yi Kuo

Krishnendu Chakrabarty

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2011

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives.

[BibT_eX]

[DOI]

Kuan-Yu Liao

Chia-Yuan Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2011

An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology.

[BibT_eX]

[DOI]

Chi-Hsuan Cheng

J. Electron. Test., 2011

Placement Optimization of Flexible TFT Digital Circuits.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2011

Test clock domain optimization for peak power supply noise reduction during scan.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2011

An at-speed self-testable technique for the high speed domino adder.

[BibT_eX]

[DOI]

Charlie Chung-Ping Chen

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay Defects.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

CSER: BISER-based concurrent soft-error resilience.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Static timing analysis for flexible TFT circuits.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

Time-space test response compaction and diagnosis based on BCH codes.

[BibT_eX]

[DOI]

F.-M. Wang

W.-C. Wang

IET Comput. Digit. Tech., 2009

Very-Low-Voltage testing of amorphous silicon TFT circuits.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

Power scan: DFT for power switches in VLSI designs.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

BIST design optimization for large-scale embedded memory cores.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Bridging Fault Diagnosis to Identify the Layer of Systematic Defects.

[BibT_eX]

[DOI]

Po-Juei Chen

Hsing Jasmine Chao

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Fault modeling and testing of retention flip-flops in low power designs.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Effective and Economic Phase Noise Testing for Single-Chip TV Tuners.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2008

Diagnosis of Multiple Scan Chain Timing Faults.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Two-level Simultaneous Test Data and Time Reduction Technique for SOC.

[BibT_eX]

[DOI]

Yu-Te Liaw

Bing-Chuan Bai

J. Inf. Sci. Eng., 2008

Simultaneous capture and shift power reduction test pattern generator for scan testing.

[BibT_eX]

[DOI]

H.-T. Lin

J. C.-M. Li

IET Comput. Digit. Tech., 2008

Survey of Scan Chain Diagnosis.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2008

Diagnosis of Logic-to-chain Bridging Faults.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores.

[BibT_eX]

[DOI]

Geng-Ming Chiu

Proceedings of the 2008 IEEE International Test Conference, 2008

On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007

Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis.

[BibT_eX]

[DOI]

Hung-Mao Lin

Fang-Min Wang

IEEE Trans. Computers, 2007

Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing.

[BibT_eX]

[DOI]

Chun-Yi Lee

J. Low Power Electron., 2007

Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis.

[BibT_eX]

[DOI]

Yu-Long Kao

Wei-Shun Chuang

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

Diagnosis of single stuck-at faults and multiple timing faults in scan chains.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Jump Scan: A DFT Technique for Low Power Testing.

[BibT_eX]

[DOI]

Min-Hao Chiu

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Column parity and row selection (CPRS): a BIST diagnosis technique for multiple errors in multiple scan chains.

[BibT_eX]

[DOI]

Hung-Mao Lin

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

ELF-Murphy Data on Defects and Test Sets.

[BibT_eX]

[DOI]

François-Fabien Ferhani

Edward Li

Subhasish Mitra

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

2002

Diagnosis of Sequence-Dependent Chips.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

2001

Diagnosis of Tunneling Opens.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Testing for resistive opens and stuck opens.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

Testing for tunneling opens.

[BibT_eX]

[DOI]