Chien-In Henry Chen

According to our database, Chien-In Henry Chen authored at least 47 papers between 1989 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Calibration of optimized minimum inductor bandpass filter with controllable bandwidth and stopband rejection.

Yu Wang, Jianfeng Ren, Chien-In Henry Chen

Integr., 2021

2020

High two-signal dynamic range and accurate frequency measurement for close frequency separation wideband digital receiver using adaptive gain control and adaptive thresholding.

Feiran Liu, Chien-In Henry Chen

Integr., 2020

2017

Chebyshev Bandpass Filter Using Resonator of Tunable Active Capacitor and Inductor.

Yu Wang, Jian Chen, Chien-In Henry Chen

VLSI Design, 2017

2016

Digital linear chirp receiver for high chirp rates with high resolution time-of-arrival and time-of-departure estimation.

Stephen Benson, Chien-In Henry Chen, David M. Lin, Lihyeh L. Liou

IEEE Trans. Aerosp. Electron. Syst., 2016

2015

Process Variation Aware Wide Tuning Band Pass Filter for Steep Roll-Off High Rejection.

Jian Chen, Chien-In Henry Chen

VLSI Design, 2015

2014

Modular test RF instrumentation and measurement for a hybrid computing digital wideband receiver.

Kiran George, Chien-In Henry Chen

Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2014

2013

Multiple Signal Detection Digital Wideband Receiver using Hardware Accelerators.

Kiran George, Chien-In Henry Chen

IEEE Trans. Aerosp. Electron. Syst., 2013

2011

A Hybrid Computing Platform Digital Wideband Receiver Design and Performance Measurement.

Kiran George, Chien-In Henry Chen

IEEE Trans. Instrum. Meas., 2011

Adaptive Thresholding for High Dual-Tone Signal Instantaneous Dynamic Range in Digital Microwave Receiver.

Stephen Benson, Chien-In Henry Chen

IEEE Trans. Instrum. Meas., 2011

Delay optimization considering power saving in dynamic CMOS circuits.

Kumar Yelamarthi, Chien-In Henry Chen

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations.

Kumar Yelamarthi, Chien-In Henry Chen

VLSI Design, 2010

2009

Dynamic Kernel Function Fast Fourier Transform With Variable Truncation Scheme for Wideband Coarse Frequency Detection.

Yu-Heng George Lee, Chien-In Henry Chen

IEEE Trans. Instrum. Meas., 2009

Logic Built-In Self-Test for Core-Based Designs on System-on-a-Chip.

Kiran George, Chien-In Henry Chen

IEEE Trans. Instrum. Meas., 2009

Dual Thresholding for Digital Wideband Receivers with Variable Truncation Scheme.

Yu-Heng George Lee, Chien-In Henry Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Structure Design and Optimization of 2-D LFSR-Based Multisequence Test Generator in Built-In Self-Test.

Xinhui Zhang, Chien-In Henry Chen, Arvindkumar Chakravarthy

IEEE Trans. Instrum. Meas., 2008

Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization.

Kumar Yelamarthi, Chien-In Henry Chen

J. Comput., 2008

Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic.

Kumar Yelamarthi, Chien-In Henry Chen

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

FPGA-Based 1.2 GHz Bandwidth Digital Instantaneous Frequency Measurement Receiver.

James Helton, Chien-In Henry Chen, David M. Lin, James B. Y. Tsui

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Real-time FPGA-based implementation of digital instantaneous frequency measurement receiver.

Yu-Heng George Lee, James Helton, Chien-In Henry Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

Built-In Self-Test for Low-Voltage High-Speed Analog-to-Digital Converters.

Jason Wibbenmeyer, Chien-In Henry Chen

IEEE Trans. Instrum. Meas., 2007

Low-Power 4-b 2.5-GSPS Pipelined Flash Analog-to-Digital Converter in 130-nm CMOS.

Mingzhen Wang, Chien-In Henry Chen, Shailesh Radhakrishnan

IEEE Trans. Instrum. Meas., 2007

Low-power 1.25-GHZ signal bandwidth 4-bit CMOS analog-to-digital converter for high spurious-free dynamic range wideband communications.

Mingzhen Wang, Chien-In Henry Chen

Proceedings of the 2007 IEEE International SOC Conference, 2007

Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization.

Kumar Yelamarthi, Chien-In Henry Chen

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2005

Design and performance evaluation of a 2.5-GSPS digital receiver.

Chien-In Henry Chen, Kiran George, William McCormick, James B. Y. Tsui, Stephen L. Hary, Keith M. Graves

IEEE Trans. Instrum. Meas., 2005

A low-power 4-b 2.5 Gsample/s pipelined flash analog-to-digital converter using differential comparator and DCVSPG encoder.

Shailesh Radhakrishnan, Mingzhen Wang, Chien-In Henry Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Configurable two-dimensional linear feedback shifter registers for parallel and serial built-in self-test.

Chien-In Henry Chen, Kiran George

IEEE Trans. Instrum. Meas., 2004

2003

Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns.

Chien-In Henry Chen, Kiran George

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST].

Chien-In Henry Chen, Kiran George

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

Timing Challenges for Very Deep Sub-Micron (VDSM) IC.

Ichiang Lin, Chien-In Henry Chen

VLSI Design, 2002

Timing-Driven-Testable Convergent Tree Adders.

Johnnie A. Huang, Chien-In Henry Chen

VLSI Design, 2002

Testability Synthesis for Jumping Carry Adders.

Chien-In Henry Chen, Mahesh Wagh

VLSI Design, 2002

Timing Analysis and Optimization for DSM IC - Guest Editorial.

Chien-In Henry Chen

VLSI Design, 2002

2001

Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults.

Chien-In Henry Chen

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

2000

Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs.

Chien-In Henry Chen, Yingjie Zhou

VLSI Design, 2000

1999

High-level design synthesis with redundancy removal for high speed testable adders.

Meghanad D. Wagh, Chien-In Henry Chen

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1994

Cluster Partitioning Techniques for Data Path Synthesis.

Chien-In Henry Chen, Gerald E. Sobelman

VLSI Design, 1994

Using PDM on Multiport Memory Allocation in Data Path.

Chien-In Henry Chen

VLSI Design, 1994

Partitioning Techniques for Built-In Self-Test Design.

Chien-In Henry Chen

VLSI Design, 1994

Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design.

Chien-In Henry Chen, Joel T. Yuen

IEEE Trans. Very Large Scale Integr. Syst., 1994

Comments on "Area-Time Optimal Adder Design".

Chien-In Henry Chen, Anup Kumar

IEEE Trans. Computers, 1994

1993

Logic partitioning to pseudo-exhaustive test for BIST design.

Chien-In Henry Chen, Joel T. Yuen

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992

Autonomous-Tol for Hardware Partitioning in a Built-in Self-Test Environment.

Chien-In Henry Chen, Joel T. Yuen, Ji-Der Lee

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Concurrent Test Scheduling in Built-In Self-Test Environment.

Chien-In Henry Chen, Joel T. Yuen

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991

Allocation of Multiport Memory with Ports of Different Type in Register Transfer Level Synthesis.

Chien-In Henry Chen

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

BISTSYN - A Built-In Self-Test Synthesizer.

Chien-In Henry Chen

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Graph Partitioning for Concurrent Test Scheduling in VLSI Circuit.

Chien-In Henry Chen

Proceedings of the 28th Design Automation Conference, 1991

1989

An efficient approach to pseudo-exhaustive test generation for BIST design.

Chien-In Henry Chen, Gerald E. Sobelman

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989