Chien-Heng Wong
According to our database1,
Chien-Heng Wong
authored at least 12 papers
between 2013 and 2019.
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Collaborative distances:
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Bibliography
2019
A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019
2018
A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
A fully integrated 28nm CMOS dual source adaptive thermoelectric and RF energy harvesting circuit with 110mv startup voltage.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection.
IEEE J. Solid State Circuits, 2017
IEEE J. Solid State Circuits, 2017
2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Invited - A 2.2 GHz SRAM with high temperature variation immunity for deep learning application under 28nm.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013