Chien-Fu Chen
Orcid: 0000-0003-3576-4118
According to our database1,
Chien-Fu Chen
authored at least 14 papers
between 2010 and 2023.
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Bibliography
2023
Developing Prediction Model of Travel Times of the Logistics Fleets of Large Convenience Store Chains Using Machine Learning.
Algorithms, June, 2023
2022
Remote. Sens., 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
2019
SECO: A Scalable Accuracy Approximate Exponential Function Via Cross-Layer Optimization.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
2017
A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme.
IEEE J. Solid State Circuits, 2017
2015
RRAM-based 7T1R nonvolatile SRAM with 2x reduction in store energy and 94x reduction in restore energy for frequent-off instant-on applications.
Proceedings of the Symposium on VLSI Circuits, 2015
17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia.
IEEE Trans. Biomed. Circuits Syst., 2014
Joint resource allocation and relay selection via genetic algorithm in multi-user decode-and-forward cooperative systems.
IET Networks, 2014
ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing.
Proceedings of the Symposium on VLSI Circuits, 2014
2012
Joint relay selection, bandwidth allocation and power distribution via genetic algorithm in multi-user decode-and-forward relay networks.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012
2011
Comput. Phys. Commun., 2011
2010
A 0.45-V 300-MHz 10T Flowthrough SRAM With Expanded write/ read Stability and Speed-Area-Wise Array for Sub-0.5-V Chips.
IEEE Trans. Circuits Syst. II Express Briefs, 2010