Chie-Min Chao

According to our database, Chie-Min Chao authored at least 6 papers between 2004 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2006

A Compact DSP Core with Static Floating-Point Arithmetic.

Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chih-Wei Jen

J. VLSI Signal Process., 2006

A 52mW 1200MIPS compact DSP for multi-core media SoC.

Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Hierarchical instruction encoding for VLIW digital signal processors.

Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A unified processor architecture for RISC & VLIW DSP.

Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004

Static floating-point unit with implicit exponent tracking for embedded DSP.

Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A compact DSP core with static floating-point unit & its microcode generation.

Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004