Chidamber Kulkarni

According to our database1, Chidamber Kulkarni authored at least 26 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
The Gluten Open-Source Software Project: Modernizing Java-based Query Engines for the Lakehouse Era.
Proceedings of the Joint Proceedings of Workshops at the 49th International Conference on Very Large Data Bases (VLDB 2023), Vancouver, Canada, August 28, 2023

2012
A lean FPGA soft processor built using a DSP block.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011
Transactional memories for multi-processor FPGA platforms.
J. Syst. Archit., 2011

2007
Configurable Transactional Memory.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

2006
Micro-Coded Datapaths: Populating the Space Between Finite State Machine and Processor.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Building a flexible and scalable DRAM interface for networking applications on FPGAs.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Memory centric thread synchronization on platform FPGAs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications.
IEEE Trans. Computers, 2005

2004
Mapping a domain specific language to a platform FPGA.
Proceedings of the 41th Design Automation Conference, 2004

Hyper-Programmable Architectures for Adaptable Networked Systems.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study.
Proceedings of the 2003 Design, 2003

Programming challenges in network processor deployment.
Proceedings of the International Conference on Compilers, 2003

2002
Developing Architectural Platforms: A Disciplined Approach.
IEEE Des. Test Comput., 2002

Data Access and Storage Management for Embedded Programmable Processors.
Kluwer, ISBN: 978-0-7923-7689-7, 2002

2001
A Systematic Approach to Reduce the System Bus Load and Power in Multimedia Algorithms.
VLSI Design, 2001

Data and memory optimization techniques for embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2001

Data Memory Organization and Optimizations in Application-Specific Systems.
IEEE Des. Test Comput., 2001

Random-Access Data Storage Components in Customized Architectures.
IEEE Des. Test Comput., 2001

A Systematic Approach for System Bus Load Reduction Applied to Medical Imaging.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Cache conscious data layout organization for embedded multimedia applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Advanced Data Layout Optimization for Multimedia Applications.
Proceedings of the Parallel and Distributed Processing, 2000

1999
System-Level Energy-Delay Exploration for Multimedia Applications on Embedded Cores with Hardware Cache.
J. VLSI Signal Process., 1999

Interaction Between Data Parallel Compilation and Data Transfer and Storage Cost Minimization for Multimedia Applications.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998
Code Transformations for Low Power Caching in Embedded Multimedia Processors.
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998

Hardware Cache Optimization for Parallel Multimedia Applications.
Proceedings of the Euro-Par '98 Parallel Processing, 1998


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