Chiara Sandionigi

According to our database1, Chiara Sandionigi authored at least 23 papers between 2007 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2019
Estimation of oxide breakdown effects by fault injection.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2017
Early estimation of aging in the design flow of integrated circuits through a programmable hardware module.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016
Fine-grain analysis of the parameters involved in aging of digital circuits.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

2015
A simulation framework for rapid prototyping and evaluation of thermal mitigation techniques in many-core architectures.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Workload-dependent BTI analysis in a processor core at high level.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Identifying aging-aware representative paths in processors.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

2014
Design of Hardened Embedded Systems on Multi-FPGA Platforms.
ACM Trans. Design Autom. Electr. Syst., 2014

Early design stage thermal evaluation and mitigation: The locomotiv architectural case.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Optimizing Service Selection and Allocation in Situational Computing Applications.
IEEE Trans. Serv. Comput., 2013

On the Simulation of HCI-Induced Variations of IC Timings at High Level.
J. Electron. Test., 2013

Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms.
J. Electron. Test., 2013

When processors get old: Evaluation of BTI and HCI effects on performance and reliability.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

2012
A reliability-aware design methodology for embedded systems on multi-FPGA platforms.
PhD thesis, 2012

Increasing autonomous fault-tolerant FPGA-based systems' lifetime.
Proceedings of the 17th IEEE European Test Symposium, 2012

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs.
IEEE Trans. Computers, 2011

A reliable fault classifier for dependable systems on SRAM-based FPGAs.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

A Reliability-Aware Partitioner for Multi-FPGA Platforms.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010
Fault Classification for SRAM-Based FPGAs in the Space Environment for Fault Mitigation.
IEEE Embed. Syst. Lett., 2010

An integrated flow for the design of hardened circuits on SRAM-based FPGAs.
Proceedings of the 15th European Test Symposium, 2010

A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA Platforms.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2007
An adaptive genetic algorithm for dynamically reconfigurable modules allocation.
Proceedings of the IFIP VLSI-SoC 2007, 2007


  Loading...