Chiao-Ling Lung

According to our database, Chiao-Ling Lung authored at least 7 papers between 2010 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability.

Hsuan-Ming Chou, Ming-Yi Hsiao, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Chiao-Ling Lung, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen

IEEE Trans. Very Large Scale Integr. Syst., 2015

2014

Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization.

Cody Hao Yu, Chiao-Ling Lung, Yi-Lun Ho, Ruei-Siang Hsu, Ding-Ming Kwai, Shih-Chieh Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013

Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs.

Chiao-Ling Lung, Yu-Shih Su, Hsih-Hsiu Huang, Yiyu Shi, Shih-Chieh Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2011

TSV fault-tolerant mechanisms with application to 3D clock networks.

Chiao-Ling Lung, Jui-Hung Chien, Yiyu Shi, Shih-Chieh Chang

Proceedings of the International SoC Design Conference, 2011

Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization.

Chiao-Ling Lung, Yi-Lun Ho, Ding-Ming Kwai, Shih-Chieh Chang

Proceedings of the Design, Automation and Test in Europe, 2011

Fault-tolerant 3D clock network.

Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu Shi, Shih-Chieh Chang

Proceedings of the 48th Design Automation Conference, 2011

2010

Clock skew optimization considering complicated power modes.

Chiao-Ling Lung, Zi-Yi Zeng, Chung-Han Chou, Shih-Chieh Chang

Proceedings of the Design, Automation and Test in Europe, 2010