Chiakang Sung

According to our database, Chiakang Sung authored at least 7 papers between 1989 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2005

A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface.

Jeffrey Tyhach, Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Yan Chong, Philip Pan, Henry Kim, Gopinath Rangan, Tzung-Chin Chang, Johnson Tan

IEEE J. Solid State Circuits, 2005

2004

A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface.

Jeffrey Tyhach, Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Yan Chong, Philip Pan, Henry Kim, Gopinath Rangan, Tzung-Chin Chang, Johnson Tan

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2000

A million gate PLD with 622 MHz I/O interface, multiple PLLs and high performance embedded CAM.

Sammy Cheung, Kar Keng Chua, Boon Jin Ang, Thow Pang Chong, Wei Lian Goay, Wei Yee Koay, Sin Wo Kuan, Chooi Pei Lim, Jiunn Shyong Oon, Theam Thye See, Chiakang Sung, Kim Pin Tan, Yu Fong Tan, Choong Kit Wong

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1998

Optimizations for a Highly Cost-Efficient Programmable Logic Architecture.

Kerry Veenstra, Bruce Pedersen, Jay Schleicher, Chiakang Sung

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

A silicon efficient FLEX 6000 programmable logic architecture.

Chiakang Sung, Richard Cliff, Joseph Huang, Bonnie Wang, Khai Nguyen, Xtaobao Wang, Kerry Veenstra, Bruce Pedersen, John Turner

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1995

Migration of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process.

John Turner, Richard Cliff, W. Leong, Cameron McClintock, Ninh Ngo, Khai Nguyen, Chiakang Sung, Bonnie Wang, J. Watson

Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995

1989

A 76-MHz BiCMOS programmable logic sequencer.

Chiakang Sung, Paul T. Sasaki, Raymond Leung, Yuet-Ming Chu, Khanh M. Le, George W. Conner, Richard H. Lane, J. L. De Jong, Ron Cline

IEEE J. Solid State Circuits, October, 1989