Chia-Yun Cheng
According to our database1,
Chia-Yun Cheng
authored at least 12 papers
between 2005 and 2018.
Collaborative distances:
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Bibliography
2018
IEEE Trans. Dependable Secur. Comput., 2018
2016
IEEE J. Solid State Circuits, 2016
A 2.6mm<sup>2</sup> 0.19nJ/pixel VP9 and multi-standard decoder LSI for Android 4K TV applications.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Energy and area efficient hardware implementation of 4K Main-10 HEVC decoder in Ultra-HD Blu-ray player and TV systems.
Proceedings of the 2015 IEEE International Conference on Multimedia and Expo, 2015
2014
Proceedings of the Symposium on VLSI Circuits, 2014
A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applications.
Proceedings of the ESSCIRC 2014, 2014
2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Area and Memory Efficient Architectures for 3D Blu-ray-compliant Multimedia Processors.
Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012
2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2005
Int. J. Electron. Bus. Manag., 2005