Chia Yee Ooi

According to our database, Chia Yee Ooi authored at least 44 papers between 2004 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

RtFog: A Real-Time FPGA-Based Fog Node With Remote Dynamically Reconfigurable Application Plane for Fog Analytics Redeployment.

Tze Hon Tan, Chia Yee Ooi, Muhammad Nadzir Marsono

IEEE Trans. Green Commun. Netw., 2022

Efficient hardware-accelerated pseudoinverse computation through algorithm restructuring for parallelization in high-level synthesis.

Chong Yeam Tan, Chia Yee Ooi, Hau Sim Choo, Nordinah Ismail

Int. J. Circuit Theory Appl., 2022

Use of learning approaches to predict clinical deterioration in patients based on various variables: a review of the literature.

Tariq Ibrahim Al-Shwaheen, Mehrdad Moghbel, Yuan Wen Hau, Chia Yee Ooi

Artif. Intell. Rev., 2022

An FPGA-based IP Core Subscription-Oriented Fog Computing Platform.

Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

2021

An FPGA-based Middlebox with Remote Dynamically Reconfigurable Application Plane.

Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono

Proceedings of the IEEE Region 10 Conference, 2021

2020

Register-Transfer-Level Features for Machine-Learning-Based Hardware Trojan Detection.

Hau Sim Choo, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail, Mehrdad Moghbel, Chee Hoo Kok

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

A review of breast boundary and pectoral muscle segmentation methods in computer-aided detection/diagnosis of breast mammography.

Mehrdad Moghbel, Chia Yee Ooi, Nordinah Ismail, Yuan Wen Hau, Nogol Memari

Artif. Intell. Rev., 2020

2019

Loop Optimizations of MGS-QRD Algorithm for FPGA High-Level Synthesis.

Chong Yeam Tan, Chia Yee Ooi, Nordinah Ismail

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Classification of Trojan Nets Based on SCOAP Values using Supervised Learning.

Chee Hoo Kok, Chia Yee Ooi, Mehrdad Moghbel, Nordinah Ismail, Hau Sim Choo, Michiko Inoue

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Evaluation of SRAM PUF Characteristics and Generation of Stable Bits for IoT Security.

Pyi Phyo Aung, Koichiro Mashiko, Nordinah Binti Ismail, Chia Yee Ooi

Proceedings of the Emerging Trends in Intelligent Computing and Informatics, 2019

Net Classification Based on Testability and Netlist Structural Features for Hardware Trojan Detection.

Chee Hoo Kok, Chia Yee Ooi, Michiko Inoue, Mehrdad Moghbel, Sreedharan Baskara Dass, Hau Sim Choo, Nordinah Ismail, Fawnizu Azmadi Hussin

Proceedings of the 28th IEEE Asian Test Symposium, 2019

Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level.

Hau Sim Choo, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail, Mehrdad Moghbel, Sreedharan Baskara Dass, Chee Hoo Kok, Fawnizu Azmadi Hussin

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018

drDRM: A PUF-Based Dynamically Reconfigurable DRM Mechanism for FPGA-Based Platform.

Tze Hon Tan, Chia Yee Ooi, Muhammad Nadzir Marsono

Proceedings of the Sixth International Symposium on Computing and Networking, 2018

2017

Ping-lock round robin arbiter.

Alireza Monemi, Chia Yee Ooi, Maurizio Palesi, Muhammad N. Marsono

Microelectron. J., 2017

Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms.

Jeevan Sirkunan, Chia Yee Ooi, Nasir Shaikh-Husin, Yuan Wen Hau, Muhammad N. Marsono

J. Syst. Archit., 2017

An integrated DFT solution for power reduction in scan test applications by low power gating scan cell.

Mahshid Mojtabavi Naeini, Sreedharan Baskara Dass, Chia Yee Ooi, Tomokazu Yoneda, Michiko Inoue

Integr., 2017

hpFog: A FPGA-Based Fog Computing Platform.

Tze Hon Tan, Chia Yee Ooi, Muhammad Nadzir Marsono

Proceedings of the 2017 International Conference on Networking, Architecture, and Storage, 2017

2016

Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC.

Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono, Maurizio Palesi

Proceedings of the 9th International Workshop on Network on Chip Architectures, 2016

SVA checker generator for FPGA-based verification platform.

Nurita Mohamad, Chia Yee Ooi, Nordinah Bt Ismail, Jwing Teh

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Power-aware through-silicon-via minimization by partitioning finite state machine with datapath.

Ayub Chin Abdullah, Chia Yee Ooi, Nordinah Bt Ismail, Nurita Binti Mohammad

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A modular architecture for dynamically reconfigurable middlebox with customized reconfiguration handler.

Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015

A Novel Scan Architecture for Low Power Scan-Based Testing.

Mahshid Mojtabavi Naeini, Chia Yee Ooi

VLSI Design, 2015

Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique.

Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono

Int. J. Reconfigurable Comput., 2015

Built-in Self Test Power and Test Time Analysis in On-chip Networks.

Mahdieh Nadi Senejani, Mahdiar Hosein Ghadiry, Chia Yee Ooi, Muhammad Nadzir Marsono

Circuits Syst. Signal Process., 2015

rrBox: A remote dynamically reconfigurable network processing middlebox.

Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Adaptive Configurable Transactional Memory for Multi-processor FPGA Platforms.

Jeevan Sirkunan, Chia Yee Ooi, Muhammad N. Shaikh-Husin, Yuan Wen Hau, Muhammad N. Marsono

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Virtual Channel and Switch Allocation for Low Latency Network-on-Chip Routers.

Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014

Thermal Model with Metal Consideration for System-on-Chip Testing.

Hasliza Hassan, Chia Yee Ooi

J. Low Power Electron., 2014

rrBox: Remote dynamically reconfigurable middlebox using NetFPGA.

Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono

Proceedings of the 14th International Symposium on Communications and Information Technologies, 2014

Remote dynamically reconfigurable platform using NetFPGA.

Tze Hon Tan, Chia Yee Ooi, Yuan Wen Hau, Nasir Shaikh-Husin, Muhammad N. Marsono

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Hardware transactional memory on multi-processor FPGA platform.

Jeevan Sirkunan, Chia Yee Ooi, Nasir Shaikh-Husin, Yuan Wen Hau, Muhammad Nadzir Marsono

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Packet logging mechanism for adaptive online fault detection on Network-on-Chip.

Ling Kim Loo, Chia Yee Ooi, V. Y. Liew, Yuan Wen Hau, Muhammad N. Marsono

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

rrBox: A Remote Dynamically Reconfigurable Middlebox for Network Protection.

Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono

Proceedings of the Second International Symposium on Computing and Networking, 2014

2013

A Semi-Analytical Approach to Study the Energy Consumption of On-Chip Networks Testing.

Mahdieh Nadi Senjani, Mahdiar Hosein Ghadiry, Chia Yee Ooi, Muhammad N. Marsono

J. Low Power Electron., 2013

Feasible transition path generation for EFSM-based system testing.

Sieng Wong, Chia Yee Ooi, Yuan Wen Hau, Muhammad N. Marsono, Nasir Shaikh-Husin

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm.

Chia Yee Ooi, Jia Pao Sua, Siaw Chen Lee

Comput. Electr. Eng., 2012

2011

A New Design-for-Testability Method Based on Thru-Testability.

Chia Yee Ooi, Hideo Fujiwara

J. Electron. Test., 2011

A Network-on-Chip simulation framework for homogeneous Multi-Processor System-on-Chip.

Yuan Wen Hau, Muhammad N. Marsono, Chia Yee Ooi, Mohamed Khalil Hani

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2008

A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models.

Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007

Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tau^k-Notation.

Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2007

2006

A New Class of Sequential Circuits with Acyclic Test Generation Complexity.

Chia Yee Ooi, Hideo Fujiwara

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A New Scan Design Technique Based on Pre-Synthesis Thru Functions.

Chia Yee Ooi, Hideo Fujiwara

Proceedings of the 15th Asian Test Symposium, 2006

2005

Classification of Sequential Circuits Based on tau^k Notation and Its Applications.

Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2005

2004

Classification of Sequential Circuits Based on ?k Notation.

Chia Yee Ooi, Hideo Fujiwara

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004