Chia-Wei Pai

According to our database, Chia-Wei Pai authored at least 6 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Design and analysis of a high-speed low-power comparator with regeneration enhancement and through current suppression techniques from 4 K to 300 K in 65-nm Cryo-CMOS.

Chia-Wei Pai, Ken Uchida, Munehiro Tada, Hiroki Ishikuro

Microelectron. J., February, 2024

A Cryo-CMOS 10-bit 60-MS/s SAR ADC with common-mode variation suppression switching scheme and gain boosting dynamic comparator.

Chia-Wei Pai, Ken Uchida, Munehiro Tada, Hiroki Ishikuro

Microelectron. J., 2024

2023

A High-Speed Low-Power Two-Stage Comparator with Regeneration Enhancement and Through Current Suppression Techniques.

Chia-Wei Pai, Hiroki Ishikuro

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2020

A Linearity Testing of Cascaded Analog Mixed-Signal Blocks Using SEIR Method.

Tatsuya Ishikawa, Chia-Wei Pai, Hiroki Ishikuro

Proceedings of the 2020 IEEE International Instrumentation and Measurement Technology Conference, 2020

2019

Enhance Algan/Gan Hemts Electrical Performance by Using Patterned Sapphire Substrate.

Chen-Kai Yi, Cheng-Yen Chien, Chien-Tsun Chan, Chia-Wei Pai, Chieh-Hsiung Kuan

Proceedings of the 2nd International Conference on Electronics, 2019

Growth Mechanism of Gan Growing on Dome-Shaped Patterned-Sapphire Substrates.

Cheng-Yen Chien, Chen Kai Yi, Chia-Wei Pai, Chiu-Chang Huang, Chieh-Hsiung Kuan

Proceedings of the 2nd International Conference on Electronics, 2019