Chia-Sheng Wen

According to our database, Chia-Sheng Wen authored at least 13 papers between 2005 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

Hierarchical Multipartite Function Evaluation.

Shen-Fu Hsiao, Chia-Sheng Wen, Yi-Hau Chen, Kuei-Chun Huang

IEEE Trans. Computers, 2017

2015

Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation.

Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Pramod Kumar Meher

IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014

Compression of Lookup Table for Piecewise Polynomial Function Evaluation.

Shen-Fu Hsiao, Chia-Sheng Wen, Po-Han Wu

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013

Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping.

Shen-Fu Hsiao, Hou-Jen Ko, Yu-Ling Tseng, Wen-Liang Huang, Shin-Hung Lin, Chia-Sheng Wen

IEEE Trans. Very Large Scale Integr. Syst., 2013

Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing units.

Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Li-Yao Chen

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2012

Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions.

Shen-Fu Hsiao, Hou-Jen Ko, Chia-Sheng Wen

IEEE Trans. Circuits Syst. II Express Briefs, 2012

Low-cost designs of rectangular to polar coordinate converters for digital communication.

Shen-Fu Hsiao, Chia-Sheng Wen, Cheng-Han Lee, Andrew Lee

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system.

Shen-Fu Hsiao, Chi-Guang Lin, Po-Han Wu, Chia-Sheng Wen

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2010

Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment.

Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Design of table-based function evaluators with reduced memory size Using a bottom-up non-uniform segmentation method.

Shen-Fu Hsiao, Chia-Sheng Wen, Kun-Chih Chen

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2008

Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction.

Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2006

Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits.

Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

An efficient pass-transistor-logic synthesizer using multiplexers and inverters only.

Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005