Chia-Jen Liang

According to our database, Chia-Jen Liang authored at least 3 papers between 2017 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS.

Yan Zhang, Chia-Jen Liang, Christopher Chen, Andrew Liu, Jason Woo, Sudhakar Pamarti, Chih-Kong Ken Yang, Mau-Chung Frank Chang

Proceedings of the 47th ESSCIRC 2021, 2021

2020

A 28-mW 32-Gb/s/pin 16-QAM Single-Ended Transceiver for High-Speed Memory Interface.

Jieqiong Du, Jia Zhou, Chia-Jen Liang, Boyu Hu, Yuan Du, Mau-Chung Frank Chang

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2017

7.1 An 802.11ac dual-band reconfigurable transceiver supporting up to four VHT80 spatial streams with 116fsrms-jitter frequency synthesizer and integrated LNA/PA delivering 256QAM 19dBm per stream achieving 1.733Gb/s PHY rate.

Tsung-Ming Chen, Yi Lu, Pang-Ning Chen, Yu-Hsien Chang, Ming-Chung Liu, Po-Yu Chang, Chia-Jen Liang, Yi-Chu Chen, Hsi-Liang Lu, Jian-Yu Ding, Chin-Chung Wang, YuLi Hsueh, Jen-Che Tsai, Min-Shun Hsu, Yuan-Hung Chung, George Chien

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017