Chia-Hsin Lee

Orcid: 0000-0002-2085-2556

According to our database1, Chia-Hsin Lee authored at least 13 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Electroencephalography Connectivity Assesses Cognitive Disorders of Autistic Children During Game-Based Social Interaction.
IEEE Trans. Cogn. Dev. Syst., April, 2024

2016
A New Methodology for Noise Sensor Placement Based on Association Rule Mining.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Improving power delivery network design by practical methodologies.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013
Enabling inter-die co-optimization in 3-D IC with TSVs.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Effective power network prototyping via statistical-based clustering and sequential linear programming.
Proceedings of the Design, Automation and Test in Europe, 2013

I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
3-D centric technology and realization with TSV.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Hierarchical power network synthesis for multiple power domain designs.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2006
SRAM Cell Current in Low Leakage Design.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

2004
Lot streaming models with a limited number of capacitated transporters in multistage batch production systems.
Comput. Oper. Res., 2004


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