Chia-Heng Yen

According to our database, Chia-Heng Yen authored at least 16 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Design and analysis of sum-prediction adder.

Chia-Heng Yen, Jin-Tai Yan

Integr., 2024

Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods.

Cheng-Che Lu, Chi-Chih Chang, Chia-Heng Yen, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao

Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

Wafer-View Defect-Pattern-Prominent GDBN Method Using MetaFormer Variant.

Shu-Wen Li, Chia-Heng Yen, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao

Proceedings of the IEEE International Test Conference, 2024

Synergizing GCN and GAT for Hardware Trojan Detection and Localization.

Yu-Chen Hsiao, Chia-Heng Yen, Bo-Yang Ke, Kai-Chiang Wu

Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2024

2023

CNN-Based Stochastic Regression for IDDQ Outlier Identification.

Chia-Heng Yen, Chun-Teng Chen, Cheng-Yen Wen, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information.

Ching-Min Liu, Chia-Heng Yen, Shu-Wen Lee, Kai-Chiang Wu, Mango Chia-Tso Chao

Proceedings of the IEEE International Test Conference, 2023

Using Path Features for Hardware Trojan Detection Based on Machine Learning Techniques.

Chia-Heng Yen, Jung-Che Tsai, Kai-Chiang Wu

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Layer-Minimization-Oriented GNR Area Routing.

Chia-Heng Yen, Jin-Tai Yan

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2021

Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks.

Cheng-Hao Yang, Chia-Heng Yen, Ting-Rui Wang, Chun-Teng Chen, Mason Chern, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

2020

CNN-based Stochastic Regression for IDDQ Outlier Identification.

Chun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

2019

Construction of Delay-Driven GNR Routing Tree.

Jin-Tai Yan, Chia-Heng Yen

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

2018

Feasible Assignment of Micro-Bumps in 3D ICs.

Jin-Tai Yan, Chia-Heng Yen

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Prediction of Metastasis in Head and Neck Cancer from Computed Tomography Images.

Tzu-Yun Lo, Pei-Yin Wei, Chia-Heng Yen, Jiing-Feng Lirng, Muh-Hwa Yang, Pen-Yuan Chu, Shinn-Ying Ho

Proceedings of the 4th International Conference on Robotics and Artificial Intelligence, 2018

2016

Cell-aware MBFF utilization for clock power reduction.

Jin-Tai Yan, Meng-Tian Chen, Chia-Heng Yen

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2014

Feasible region assignment of routing nets in single-layer routing.

Jin-Tai Yan, Yu-Jen Tseng, Chia-Heng Yen

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Efficient micro-bump assignment for RDL routing in 3DICs.

Jin-Tai Yan, Yu-Jen Tseng, Chia-Heng Yen

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014